Apparatus and method for over-voltage protection

• US 10,693,450 B2
• Filed: 06/28/2018
• Issued: 06/23/2020
• Est. Priority Date: 06/28/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Nedalgi, Dharmaray, Ns, Karthik, Deshpande, Vani, Heiss, Leonhard
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US16/022,555
• Publication Number:
  US 20200007120A1
• Time in Patent Office: 726 Days
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

An apparatus is provided which comprises: a dual stack voltage driver, wherein the dual stack voltage driver comprises a first stack of transistors, and a second stack of transistors; and one or more feedback transistors each coupled to a transistor of the second stack of transistors.

Claims

1. An apparatus comprising:

a first power supply rail to provide a first power supply;

a second power supply rail to provide a second power supply, wherein the first power supply is higher than the second power supply, wherein a voltage level of the first power supply and a voltage level of the second power supply are higher than a ground voltage on a ground power supply rail;

a first stack of transistors of a same conductivity type, the first stack including a first transistor and a second transistor coupled in series and having a first common node, wherein the first transistor is coupled to the first power supply rail;

a second stack of transistors of an opposite conductivity type to the first stack of transistors, the second stack including a third transistor and a fourth transistor coupled in series and having a second common node, wherein the second stack of transistor is coupled in series to the first stack of transistors and having a third common node, wherein a gate terminal of the third transistor is coupled to a circuitry which is coupled to the second power supply rail; and

a feedback transistor of a same conductivity type of the third transistor coupled to the second common node and a gate terminal of the third transistor of the second stack, wherein the feedback transistor includes a gate terminal which is coupled to the third common node.

2. The apparatus of claim 1, wherein the gate terminal of the third transistor, and a gate terminal of the fourth transistor are controllable by two separate control nodes.

3. The apparatus of claim 2, wherein the gate terminal of the third transistor is coupled to a second power rail via the circuitry.

4. The apparatus of claim 1, wherein a gate terminal of the first transistor is coupled to an input voltage, and a gate terminal of the second transistor is couple to a bias voltage.

5. The apparatus of claim 1, wherein the feedback transistor is smaller in size than the third transistor.

6. The apparatus of claim 1, wherein the feedback transistor comprises an n-type transistor.

7. The apparatus of claim 1, further comprising a capacitor which is coupled with the gate of the third transistor and the gate of the fourth transistor.

8. The apparatus of claim 7, wherein a size of the capacitor is proportional to a size of the third transistor.

9. A system comprising:

a memory;

a processor coupled to the memory, the processor including;

a first power supply rail to provide a first power supply;

a second power supply rail to provide a second power supply, wherein the first power supply is higher than the second power supply, wherein a voltage level of the first power supply and a voltage level of the second power supply are higher than a ground voltage on a ground power supply rail;

a first stack of transistors of a same conductivity type, the first stack including a first transistor and a second transistor coupled in series and having a first common node, wherein the first transistor is coupled to the first power supply rail;

a second stack of transistors of an opposite conductivity type to the first stack of transistors, the second stack including a third transistor and a fourth transistor coupled in series and having a second common node, and wherein the second stack of transistor is coupled in series to the first stack of transistors and having a third common node,and wherein a gate terminal of the third transistor is coupled to a circuitry which is coupled to the second power supply rail;

a feedback transistor of a same conductivity type of the third transistor coupled to the second common node and a gate terminal of the third transistor of the second stack;

a capacitor coupled with the gate of the third transistor and the gate of the fourth transistor; and

a wireless interface to allow the processor to communicate with another device.

10. The system of claim 9, wherein the feedback transistor includes a gate terminal which is coupled to the third common node.

11. The system of claim 9, wherein the gate terminal of the third transistor, and a gate terminal of the fourth transistor are controllable by two separate control nodes.

12. The system of claim 11, wherein the gate terminal of the third transistor is coupled to a second power rail via a pass-gate circuitry.

13. An apparatus comprising:

a dual stack voltage driver, wherein the dual stack voltage driver comprises a first stack of transistors, and a second stack of transistors, wherein the second stack of transistors is coupled in series to the first stack of transistors; and

one or more feedback transistors each coupled to a transistor of the second stack of transistors,

wherein each of the gate terminals of the transistors of the second stack transistors are controlled by a separate control node.

14. The apparatus of claim 13, wherein each second stack transistor and its adjacent second stack transistor are coupled at a first common node, and wherein the one or more feedback transistors coupled to the second stack transistor includes a gate terminal which is coupled to the first common node.

15. The apparatus of claim 13, wherein each of the one or more feedback transistors is coupled to the gate of a second stack transistor, and is coupled to a second common node of the second stack transistor.

16. The apparatus of claim 13, wherein each of the gate terminals of the transistors of the second stack of transistors are coupled to a separate power rail via a pass-gate circuitry.

17. The apparatus of claim 16, wherein each feedback transistor of the one or more feedback transistors is smaller in size than the second stack transistor to which it is coupled.

18. The apparatus of claim 16, wherein the one or more feedback transistors comprise one or more n-type transistors.

19. The apparatus of claim 16, wherein the dual stack voltage driver includes one or more capacitors, wherein each capacitor of the one or more capacitors is coupled with the gate of a second stack transistor, and wherein the capacitor size is proportional to the size of the second stack transistor to which it is coupled.

20. An apparatus comprising:

a dual stack voltage driver, wherein the dual stack voltage driver comprises a first stack of transistors, and a second stack of transistors, wherein the second stack of transistors is coupled in series to the first stack of transistors; and

one or more feedback transistors each coupled to a transistor of the second stack of transistors,

wherein each second stack transistor and its adjacent second stack transistor are coupled at a first common node, and wherein the one or more feedback transistors coupled to the second stack transistor includes a gate terminal which is coupled to the first common node.

21. The apparatus of claim 20, wherein each of the gate terminals of the transistors of the second stack transistors are controlled by a separate control node.