Infinite memory fabric hardware implementation with memory

• US 10,698,628 B2
• Filed: 05/31/2016
• Issued: 06/30/2020
• Est. Priority Date: 06/09/2015
• Status: Active Grant

• Current Assignee: Ultrata, LLC
• Original Assignee: Ultrata, LLC
• Inventors: Frank, Steven J., Reback, Larry
• Primary Examiner(s): Song, Hua J
• Application Number:
  US15/169,580
• Publication Number:
  US 20160364172A1
• Time in Patent Office: 1,491 Days
• Field of Search: 711165
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/54 Interprogram communication

Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein the first memory has a lower latency than the second memory, and wherein each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions, wherein a set of data is stored within the first memory of the memory module; wherein the memory module is configured to receive an indication of a subset of the set of data that is eligible to be transferred between the first memory and the second memory; and wherein the memory module dynamically determines which of the subset of data will be transferred to the second memory based on access patterns associated with the object memory fabric.

Claims

1. A hardware-based processing node of an object memory fabric, the processing node comprising:

a memory module storing and managing one or more memory objects, the memory module comprising at least a Field Programmable Gate Array (FPGA), a first memory, and a second memory, wherein the first memory has a lower latency than the second memory, and wherein;

each memory object is created natively within the memory module,

each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions,

a first set of data of the one or more memory objects is stored within the first memory of the memory module and a second set of data of the one or more memory objects is stored within the second memory of the memory module, and

the FPGA of the memory module dynamically determines during execution of one or more applications on the hardware-based processing node at a hardware level of the memory module which of the first subset of data will be transferred to the second memory and dynamically determines during continued execution of the one or more applications which of the second subset of data will be transferred to the first memory based on access patterns associated with the object memory fabric.

2. The hardware-based processing node of claim 1, wherein the FPGA of the memory module initiates the transfer of the first subset of data and the second subset of data.

3. The hardware-based processing node of claim 2, wherein the FPGA of the memory module transmits a communication to a processor connected to the hardware-based processing node, wherein the communication includes a notification that data has been transferred to the second memory.

4. The hardware-based processing node of claim 1, wherein a data of the second subset of data is eligible to be transferred between to the first memory from the second memory based on a determination that the data will be referenced within a certain predetermined period of time.

5. The hardware-based processing node of claim 1, wherein dynamically determining which of the first subset of data will be transferred to the second memory includes using metadata stored in the memory module, wherein the metadata is associated with the data.

6. The hardware-based processing node of claim 1, wherein the first memory is a non-volatile, persistent memory and the second memory is a volatile, non-persistent memory.

7. The hardware-based processing node of claim 6, wherein the memory module comprises a single Dual In-line Memory Module (DIMM) and wherein the first memory is a flash memory and the second memory is a dynamic random-access memory (DRAM).

8. The hardware-based processing node of claim 7, wherein the FPGA of the memory module maps an object of the one or more memory objects from the object memory fabric into a virtual address space and from the virtual address space into a physical memory address pace of the first memory and the second memory.

9. The hardware-based processing node of claim 1, wherein the memory module is a single Dual In-line Memory Module (DIMM) and comprises an accelerator module storing the one or more memory objects, wherein the accelerator module performs a set of predefined management functions on the one or more memory objects.

10. The hardware-based processing node of claim 9, wherein the set of predefined management functions of the accelerator module replace storage management and networking software in the node.

11. An object memory fabric comprising:

a plurality of hardware-based processing nodes, each hardware-based processing node comprising;

a memory module storing and managing one or more memory objects, the memory module comprising at least a Field Programmable Gate Array (FPGA), a first memory, and a second memory, wherein the first memory has a lower latency than the second memory, and wherein;

each memory object is created natively within the memory module,

each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions,

a first set of data of the one or more memory objects is stored within the first memory of the memory module and a second set of data of the one or more memory objects is stored within the second memory of the memory module, and

the FPGA of the memory module dynamically determines during execution of one or more applications on the hardware-based processing node at a hardware level of the memory module which of the first subset of data will be transferred to the second memory and dynamically determines during continued execution of the one or more applications which of the second subset of data will be transferred to the first memory based on access patterns associated with the object memory fabric.

12. The object memory fabric of claim 11, wherein the FPGA of the memory module initiates the transfer of the first subset of data and the second subset of data.

13. The object memory fabric of claim 12, wherein the FPGA of the memory module transmits a communication to a processor connected to the hardware-based processing node, wherein the communication includes a notification that data has been transferred to the second memory.

14. The object memory fabric of claim 11, wherein a data of the second subset of data is eligible to be transferred between to the first memory from the second memory based on a determination that the data will be referenced within a certain predetermined period of time.

15. The object memory fabric of claim 11, wherein dynamically determining which of the first subset of data will be transferred to the second memory includes using metadata stored in the memory module, wherein the metadata is associated with the data.

16. The object memory fabric of claim 11, wherein the first memory is a non-volatile, persistent memory and the second memory is a volatile, non-persistent memory.

17. The object memory fabric of claim 16, wherein each memory module comprises a single Dual In-line Memory Module (DIMM) and wherein the first memory is a flash memory and the second memory is a dynamic random-access memory (DRAM).

18. The object memory fabric of claim 17, wherein the FPGA of each memory module maps an object of the one or more memory objects from the object memory fabric into a virtual address space and maps the object from the virtual address space into a physical memory address space of the first memory and the second memory.

19. The object memory fabric of claim 11, wherein the memory module is a single Dual In-line Memory Module and comprises an accelerator module storing the one or more memory objects, wherein the accelerator module performs a set of predefined management functions on the one or more memory objects.

20. The object memory fabric of claim 19, wherein the set of predefined management functions of the accelerator module replace storage management and networking software in the node.

21. A computer-implemented method, comprising:

creating one or more memory objects natively within a memory module of a hardware-based processing node of the object memory fabric, wherein the hardware-based processing node includes a memory module storing and managing one or more memory objects, the memory module comprising at least a Field Programmable Gate Array (FPGA), a first memory, and a second memory, the first memory having lower latency than the second memory;

accessing each memory object of the one or more memory objects using a single memory reference instruction without Input/Output (I/O) instructions; and

storing, by the hardware-based processing node, a first set of data of the one or more memory objects within the first memory of the memory module;

storing, by the hardware-based processing node, a second set of data of the one or more memory objects within the second memory of the memory module;

determining, by the FPGA of the memory module at a hardware level of the memory module during execution of one or more applications on the hardware-based processing node, which of the first subset of data will be transferred to the second memory based on access patterns associated with the object memory fabric; and

determining, by the FPGA of the memory module at a hardware level of the memory module during continued execution of one or more applications on the hardware-based processing node, which of the second subset of data will be transferred to the first memory based on access patterns associated with the object memory fabric.

22. The method of claim 21, wherein the FPGA of the memory module initiates the transfer of the first subset of data and the second subset of data.

23. The method of claim 22, wherein the FPGA of the memory module transmits a communication to a processor connected to the hardware-based processing node, wherein the communication includes a notification that data has been transferred to the second memory.

24. The method of claim 21, wherein a data of the second subset of data is eligible to be transferred between to the first memory from the second memory based on a determination that the data will be referenced within a certain predetermined period of time.

25. The method of claim 21, wherein dynamically determining which of the first subset of data will be transferred to the second memory includes using metadata stored in the memory module, wherein the metadata is associated with the data.

26. The method of claim 21, wherein the first memory is a non-volatile, persistent memory and the second memory is a volatile, non-persistent memory.

27. The method of claim 26, wherein the memory module comprises a single Dual In-line Memory Module (DIMM) and wherein the first memory is a flash memory and the second memory is a dynamic random-access memory (DRAM).

28. The method of claim 27, the FPGA of the memory module maps an object of the one or more memory objects from the object memory fabric into a virtual address space and from the virtual address space into a physical memory address space of the first memory and the second memory.

29. The method of claim 21, wherein the memory module is a single Dual In-line Memory Module (DIMM) and comprises an accelerator module storing the one or more memory objects, wherein the accelerator module performs a set of predefined management functions on the one or more memory objects.

30. The method of claim 29, wherein the set of predefined management functions of the accelerator module replace storage management and networking software in the node.