Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

• US 10,698,640 B2
• Filed: 12/13/2017
• Issued: 06/30/2020
• Est. Priority Date: 08/12/2013
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Prather, Matthew A.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US15/841,126
• Publication Number:
  US 20180107433A1
• Time in Patent Office: 930 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Claims

1. A method, comprising:

receiving, at a memory module, a command initiated by a host device to operate the memory module in a mode that is based at least in part on a power failure event, wherein the mode of operation comprises communicating data from a synchronous dynamic random-access memory (SDRAM) of the memory module to a non-volatile memory (NVM) of the memory module for the power failure event;

transferring the data from the SDRAM to the NVM via a control circuit of the memory module in response to the command; and

programming, by the memory module, a mode register of the SDRAM with information that configures the SDRAM to operate according to the mode of operation, wherein the programming is based at least in part on transferring the data from the SDRAM to the NVM;

avoiding command signaling from the host while in the mode of operation; and

transferring the data from the NVM back to the SDRAM via the control circuit based at least in part on a reapplication of power to the memory module.

2. The method of claim 1, further comprising resuming another mode of operation based at least in part on a reapplication of power to the memory module.

3. The method of claim 2, wherein the other mode of operation comprises restoring the data from the NVM to the SDRAM via the control circuit based at least in part on the reapplication of power to the memory module.

4. The method of claim 1, further comprising receiving, at the memory module, another command initiated by the host device to operate the memory module in another mode that is different from the mode of operation that comprises communicating data from the SDRAM to the NVM.

5. The method of claim 4, wherein the other command is initiated after power is re-applied to the memory module.

6. The method of claim 4, further comprising restoring the data from the SDRAM to the NVM based at least in part on the other command and a reapplication of power to the memory module.

7. An apparatus, comprising:

a synchronous dynamic random-access memory (SDRAM);

a non-volatile memory (NVM) coupled with the SDRAM;

a control circuit coupled between the NVM and the SDRAM and configured operate in a plurality of modes and to transfer the data from the SDRAM to the NVM via the control circuit in response to a power failure event; and

a mode register coupled with the SDRAM and programmable, by the control circuit, with information that configures the SDRAM to operate according to one of the modes of operation based at least in part on the power failure event,

wherein the control circuit is configured to transfer the data from the NVM back to the SDRAM based at least in part on a reapplication of power to the apparatus.

8. The apparatus of claim 7, wherein the SDRAM is configured to avoid command signaling from a host device while the apparatus is one of the modes of operation and based at least in part on the power failure event.

9. The apparatus of claim 7, wherein the control circuit is configured to resume another mode of operation based at least in part on a reapplication of power to the apparatus.

10. The apparatus of claim 9, wherein the control circuit is configured to restore the data from the NVM to the SDRAM based at least in part on the reapplication of power to the memory module.

11. The apparatus of claim 7, wherein the control circuit is configured to receive another command initiated by the host device based at least in part on a reapplication of power to the apparatus.

12. An apparatus, comprising:

a controller configured to receive a command initiated by a host device to operate in a mode that is based at least in part on a power failure event, wherein the mode of operation comprises communicating data from a synchronous dynamic random-access memory (SDRAM) to a non-volatile memory (NVM) for the power failure event;

a plurality of SDRAMs coupled with the control logic;

an NVM coupled with the plurality of SDRAMs via the control logic; and

a plurality of mode registers coupled with the SDRAMs and programmable, by the controller, with information that configures the plurality of SDRAMs to operate according to the mode of operation of a plurality of modes of operation,

wherein the controller is configured to;

transfer the data from the plurality of SDRAMs to the NVM based at least in part on the power failure event; and

transfer the data from the NVM to one or more SDRAMs of the plurality of SDRAMs based at least in part on a reapplication of power to the circuit.

13. The apparatus of claim 12, further comprising an interface for the host device, wherein the interface is operable to avoid communication with the host device during the power failure event.

14. The apparatus of claim 13, wherein the interface is operable to receive commands from the host device based at least in part on a reapplication of power to the device.

15. The apparatus of claim 12, wherein the controller is operable to resume operating in a mode of the plurality of modes of operation based at least in part on a reapplication of power to the circuit.

16. The circuit of claim 15, wherein the SDRAM is configured to communicate with the host via a bus while operating in a first mode of the plurality of modes of operation and to refrain from communication with the host while in a second mode of the plurality of modes of operation.