Memory allocation system for multi-tier memory

• US 10,698,813 B2
• Filed: 07/12/2018
• Issued: 06/30/2020
• Est. Priority Date: 12/09/2016
• Status: Active Grant

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Poxon, Heidi Lynn, Homer, William, Oehmke, David W., DeRose, Luiz, Andreasen, Clayton D., Mehta, Sanyam
• Primary Examiner(s): Choe, Yong J
• Application Number:
  US16/034,216
• Publication Number:
  US 20180322064A1
• Time in Patent Office: 719 Days
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3452 Performance evaluation by statistical analysis
• CPC Class Codes: G06F 11/3471 Address tracing
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/465 Structured object, e.g. database record
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.

Claims

1. A method performed by a computer system for collecting execution statistics of a program, the method comprising:

during execution of the program,

specifying an event for collecting statistics upon occurrences of the event;

upon an occurrence of the event,

retrieving an instruction address of a load instruction associated with the event;

retrieving a data address of data of the load instruction associated with the event;

collecting memory request statistics associated with the event;

collecting memory bandwidth utilization statistics associated with the event; and

associating with the occurrence of the event the instruction address, the data address, the memory request statistics, and the memory bandwidth utilization statistics as collected statistics for the occurrence of the event; and

during execution of the program or after execution of the program;

accessing a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are allocated; and

associating the collected statistics for an occurrence of the event with the data structure whose memory addresses include the data address associated with the event.

2. The method of claim 1, wherein the steps of

accessing the data structure map, and

associating the collected statistics are performed during execution of the program.

3. The method of claim 1 wherein the steps of

accessing the data structure map, and

associating the collected statistics are performed after execution of the program.

4. The method of claim 1 wherein an event occurs when a threshold level of a performance counter is reached.

5. The method of claim 4 wherein the performance counter is the number of last level cache misses since the last occurrence of the event.

6. The method of claim 1 wherein the event occurs at time intervals.

7. The method of claim 1 wherein the memory request statistics include the number of last level cache misses since the last occurrence of the event.

8. The method of claim 7 wherein the memory request statistics further include the number of last level cache hits since the last occurrence of the event.

9. The method of claim 8 wherein the memory bandwidth utilization statistics include the number of instructions executed since the last occurrence of the event.

10. The method of claim 9 wherein the memory bandwidth utilization statistics include a time of the occurrence of the event.

11. The method of claim 9 wherein the memory bandwidth utilization statistics include the number of processor cycles since the last occurrence of the event.

12. The method of claim 9 wherein the memory bandwidth utilization statistics include the number of processor-stalled cycles since the last occurrence of the event.

13. The method of claim 1 wherein the memory bandwidth utilization statistics include a time of the occurrence of the event.

14. The method of claim 1 wherein the memory bandwidth utilization statistics include the number of processor cycles since the last occurrence of the event.

15. A computing system for collecting execution statistics of a program, the computing system comprising:

one or more computer-readable storage mediums storing computer-executable instructions for controlling the computing system to;

upon an occurrence of the event,

retrieve an instruction address of a load instruction associated with the event;

retrieve a data address of data of the load instruction associated with the event;

collect memory statistics associated with the event; and

associate with the occurrence of the event the instruction address, the data address, and the memory statistics, as collected statistics for the occurrence of the event;

access a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are allocated; and

associate the collected memory statistics for an occurrence of the event with the data structure whose memory addresses include the data address associated with the event; and

one or more processors for executing the computer-executable instructions stored in the one or more computer-readable storage mediums.

16. The computing system of claim 15 wherein an event occurs when a threshold level of a performance counter is reached.

17. The computing system of claim 16 wherein the performance counter is the number of last level cache misses since the last occurrence of the event.

18. The computing system of claim 15 wherein the event occurs at time intervals.

19. The computing system of claim 15 wherein the memory statistics include the number of last level cache misses since the last occurrence of the event.

20. The computing system of claim 15 wherein the memory statistics include bandwidth utilization statistics.

21. The computing system of claim 15 wherein the memory statistics include memory request statistics.

22. The computing system of claim 15 wherein the memory statistics include bandwidth utilization statistics and memory request statistics.