Cycle control circuits
First Claim
Patent Images
1. A cycle control circuit comprising:
- a judgement pulse generation circuit configured to set a predetermined value in response to an initialization signal and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses;
a detection signal generation circuit configured to generate a detection signal from a reference flag in response to the judgement pulse; and
a code generation circuit configured to generate a calibration code for controlling a cycle of a reference signal in response to the detection signal and the judgement pulse,wherein the judgement pulse generation circuit is configured to initialize a count signal in response to a set control signal and a reset control signal which are generated from the initialization signal while a period signal is disabled and is configured to generate the judgement pulse by counting the count signal in response to a clock pulse which is generated from the clock signal while the period signal is enabled;
wherein the count signal is initialized by the set control signal and the reset control signal to have an initial logic level combination; and
wherein the count signal is sequentially counted from the initial logic level combination to a target logic level combination in response to the clock pulse.
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Abstract
A cycle control circuit may include a judgement pulse generation circuit, a detection signal generation circuit or a flag generation circuit. The judgement pulse generation circuit may be configured to set a predetermined value based on an initialization signal and a period signal, and to generate a judgment pulse. The detection signal generation circuit may be configured to generate a detection signal from a reference flag. The flag generation circuit may be configured to generate a reference flag based on a reference signal. A cycle of the reference signal may be maintained or adjusted based on the reference flag.
5 Citations
26 Claims
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1. A cycle control circuit comprising:
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a judgement pulse generation circuit configured to set a predetermined value in response to an initialization signal and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses; a detection signal generation circuit configured to generate a detection signal from a reference flag in response to the judgement pulse; and a code generation circuit configured to generate a calibration code for controlling a cycle of a reference signal in response to the detection signal and the judgement pulse, wherein the judgement pulse generation circuit is configured to initialize a count signal in response to a set control signal and a reset control signal which are generated from the initialization signal while a period signal is disabled and is configured to generate the judgement pulse by counting the count signal in response to a clock pulse which is generated from the clock signal while the period signal is enabled; wherein the count signal is initialized by the set control signal and the reset control signal to have an initial logic level combination; and wherein the count signal is sequentially counted from the initial logic level combination to a target logic level combination in response to the clock pulse. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A cycle control circuit comprising:
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a judgement pulse generation circuit configured to set a predetermined value in response to an initialization signal and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses; a flag generation circuit configured to generate a reference flag in response to a period signal and a reference signal, the reference signal having a cycle that is controlled by a calibration code; and a code generation circuit configured to generate the calibration code and a sense code in response to the judgement pulse and a detection signal generated from the reference flag, wherein the judgement pulse generation circuit is configured to initialize a count signal to have an initial logic level combination in response to a set control signal and a reset control signal which are generated from the initialization signal while the period signal is disabled and is configured to generate the judgement pulse by sequentially counting the count signal from the initial logic level combination to a target logic level combination in response to a clock pulse which is generated from the clock signal while the period signal is enabled. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A cycle control circuit comprising:
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a judgement pulse generation circuit configured to set a predetermined value based on an initialization signal and a period signal, and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses; and a flag generation circuit configured to generate a reference flag based on the period signal and a reference signal, wherein a cycle of the reference signal is maintained at a constant value after an operation for adjusting the cycle of the reference signal terminates based on the reference flag, wherein the judgement pulse generation circuit is configured to initialize a count signal to have an initial logic level combination in response to a set control signal and a reset control signal which are generated from the initialization signal while the period signal is disabled and is configured to generate the judgement pulse by sequentially counting the count signal from the initial logic level combination to a target logic level combination in response to a clock pulse which is generated from the clock signal while the period signal is enabled. - View Dependent Claims (21, 22)
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23. A cycle control circuit comprising:
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a judgement pulse generation circuit configured to set a predetermined value based on an initialization signal and a period signal, and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses; and a detection signal generation circuit configured to generate a detection signal from a reference flag in response to the judgement pulse, the reference flag generated based on a reference signal and the period signal, wherein a cycle of the reference signal is maintained at a constant value after an operation for adjusting the cycle of the reference signal terminates based on the reference flag; wherein the judgement pulse generation circuit is configured to initialize a count signal to have an initial logic level combination in response to a set control signal and a reset control signal which are generated from the initialization signal while the period signal is disabled and is configured to generate the judgement pulse by sequentially counting the count signal from the initial logic level combination to a target logic level combination in response to a clock pulse which is generated from the clock signal while the period signal is enabled. - View Dependent Claims (24, 25, 26)
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Specification