Neural network classifier using array of two-gate non-volatile memory cells

• US 10,699,779 B2
• Filed: 04/11/2019
• Issued: 06/30/2020
• Est. Priority Date: 11/29/2017
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van, Lemke, Steven, Tiwari, Vipin, Do, Nhan, Reiten, Mark
• Primary Examiner(s): Le, Vu A
• Application Number:
  US16/382,013
• Publication Number:
  US 20190237136A1
• Time in Patent Office: 446 Days
• Field of Search: 3651852
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

Claims

1. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises;

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a first gate having a first portion disposed over and insulated from a second portion of the channel region;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises;

a plurality of first lines each electrically connecting together the first gates in one of the rows of the memory cells;

a plurality of second lines each electrically connecting together the source regions in one of the rows of the memory cells;

a plurality of third lines each electrically connecting together the drain regions in one of the columns of the memory cells;

wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of third lines, and to provide the first plurality of outputs as electrical currents on the plurality of second lines.

2. The neural network device of claim 1, wherein for each of the plurality of memory cells, the first gate includes a second portion that extends up and over the floating gate.

3. The neural network device of claim 1, further comprising:

a first plurality of neurons configured to receive the first plurality of outputs.

4. The neural network device of claim 3, further comprising:

a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate therefrom a second plurality of outputs, wherein the second plurality of synapses comprises;

a plurality of second memory cells, wherein each of the second memory cells includes spaced apart second source and second drain regions formed in the semiconductor substrate with a second channel region extending there between, a second floating gate disposed over and insulated from a first portion of the second channel region and a second gate having a first portion disposed over and insulated from a second portion of the second channel region;

each of the plurality of second memory cells is configured to store a second weight value corresponding to a number of electrons on the second floating gate;

the plurality of second memory cells are configured generate the second plurality of outputs based upon the second plurality of inputs and the stored second weight values;

wherein the second memory cells of the second plurality of synapses are arranged in rows and columns, and wherein the second plurality of synapses comprises;

a plurality of fourth lines each electrically connecting together the second gates in one of the rows of the second memory cells;

a plurality of fifth lines each electrically connecting together the second source regions in one of the rows of the second memory cells;

a plurality of sixth lines each electrically connecting together the second drain regions in one of the columns of the second memory cells;

wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of sixth lines, and to provide the second plurality of outputs as electrical currents on the plurality of fifth lines.

5. The neural network device of claim 4, wherein for each of the plurality of second memory cells, the second gate includes a second portion that extends up and over the second floating gate.

6. The neural network device of claim 4, further comprising:

a second plurality of neurons configured to receive the second plurality of outputs.

7. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises;

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a first gate having a first portion disposed over and insulated from a second portion of the channel region;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises;

a plurality of first lines each electrically connecting together the first gates in one of the rows of the memory cells;

a plurality of second lines each electrically connecting together the source regions in one of the rows of the memory cells;

a plurality of third lines each electrically connecting together the drain regions in one of the columns of the memory cells;

wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of second lines or on the plurality of first lines, and to provide the first plurality of outputs as electrical currents on the plurality of third lines.

8. The neural network device of claim 7, wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of second lines.

9. The neural network device of claim 7, wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of first lines.

10. The neural network device of claim 7, wherein for each of the plurality of memory cells, the first gate includes a second portion that extends up and over the floating gate.

11. The neural network device of claim 7, further comprising:

a first plurality of neurons configured to receive the first plurality of outputs.

12. The neural network device of claim 11, further comprising:

a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate therefrom a second plurality of outputs, wherein the second plurality of synapses comprises;

a plurality of second memory cells, wherein each of the second memory cells includes spaced apart second source and second drain regions formed in the semiconductor substrate with a second channel region extending there between, a second floating gate disposed over and insulated from a first portion of the second channel region and a second gate having a first portion disposed over and insulated from a second portion of the second channel region;

each of the plurality of second memory cells is configured to store a second weight value corresponding to a number of electrons on the second floating gate;

the plurality of second memory cells are configured generate the second plurality of outputs based upon the second plurality of inputs and the stored second weight values;

wherein the second memory cells of the second plurality of synapses are arranged in rows and columns, and wherein the second plurality of synapses comprises;

a plurality of fourth lines each electrically connecting together the second gates in one of the rows of the second memory cells;

a plurality of fifth lines each electrically connecting together the second source regions in one of the rows of the second memory cells;

a plurality of sixth lines each electrically connecting together the second drain regions in one of the columns of the second memory cells;

wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of fifth lines or on the plurality of fourth lines, and to provide the second plurality of outputs as electrical currents on the plurality of sixth lines.

13. The neural network device of claim 12, wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of fifth lines.

14. The neural network device of claim 12, wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of fourth lines.

15. The neural network device of claim 12, wherein for each of the plurality of second memory cells, the second gate includes a second portion that extends up and over the second floating gate.

16. The neural network device of claim 12, further comprising:

a second plurality of neurons configured to receive the second plurality of outputs.

17. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises;

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a first gate having a first portion disposed over and insulated from a second portion of the channel region;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises;

a plurality of first lines each electrically connecting together the first gates in one of the rows of the memory cells;

a plurality of second lines each electrically connecting together the source regions in one of the rows of the memory cells;

a plurality of third lines each electrically connecting together the drain regions in one of the columns of the memory cells;

a plurality of transistors each electrically connected in series with one of the third lines;

wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on gates of the plurality of transistors, and to provide the first plurality of outputs as electrical currents on the plurality of second lines.

18. The neural network device of claim 17, wherein for each of the plurality of memory cells, the first gate includes a second portion that extends up and over the floating gate.

19. The neural network device of claim 17, further comprising:

a first plurality of neurons configured to receive the first plurality of outputs.

20. The neural network device of claim 19, further comprising:

a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate therefrom a second plurality of outputs, wherein the second plurality of synapses comprises;

a plurality of second memory cells, wherein each of the second memory cells includes spaced apart second source and second drain regions formed in the semiconductor substrate with a second channel region extending there between, a second floating gate disposed over and insulated from a first portion of the second channel region and a second gate having a first portion disposed over and insulated from a second portion of the second channel region;

each of the plurality of second memory cells is configured to store a second weight value corresponding to a number of electrons on the second floating gate;

the plurality of second memory cells are configured generate the second plurality of outputs based upon the second plurality of inputs and the stored second weight values;

wherein the second memory cells of the second plurality of synapses are arranged in rows and columns, and wherein the second plurality of synapses comprises;

a plurality of fourth lines each electrically connecting together the second gates in one of the rows of the second memory cells;

a plurality of fifth lines each electrically connecting together the second source regions in one of the rows of the second memory cells;

a plurality of sixth lines each electrically connecting together the second drain regions in one of the columns of the second memory cells;

a second plurality of transistors each electrically connected in series with one of the sixth lines;

wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on gates of the second plurality of transistors, and to provide the second plurality of outputs as electrical currents on the plurality of fifth lines.

21. The neural network device of claim 20, wherein for each of the plurality of second memory cells, the second gate includes a second portion that extends up and over the second floating gate.

22. The neural network device of claim 20, further comprising:

a second plurality of neurons configured to receive the second plurality of outputs.

23. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises;

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a first gate having a first portion disposed over and insulated from a second portion of the channel region;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises;

a plurality of first lines each electrically connecting together the first gates in one of the columns of the memory cells;

a plurality of second lines each electrically connecting together the source regions in one of the rows of the memory cells;

a plurality of third lines each electrically connecting together the drain regions in one of the columns of the memory cells;

wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of first lines, and to provide the first plurality of outputs as electrical currents on the plurality of second lines.

24. The neural network device of claim 23, wherein for each of the plurality of memory cells, the first gate includes a second portion that extends up and over the floating gate.

25. The neural network device of claim 23, further comprising:

a first plurality of neurons configured to receive the first plurality of outputs.

26. The neural network device of claim 25, further comprising:

a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate therefrom a second plurality of outputs, wherein the second plurality of synapses comprises;

a plurality of second memory cells, wherein each of the second memory cells includes spaced apart second source and second drain regions formed in the semiconductor substrate with a second channel region extending there between, a second floating gate disposed over and insulated from a first portion of the second channel region and a second gate having a first portion disposed over and insulated from a second portion of the second channel region;

each of the plurality of second memory cells is configured to store a second weight value corresponding to a number of electrons on the second floating gate;

the plurality of second memory cells are configured generate the second plurality of outputs based upon the second plurality of inputs and the stored second weight values;

wherein the second memory cells of the second plurality of synapses are arranged in rows and columns, and wherein the second plurality of synapses comprises;

a plurality of fourth lines each electrically connecting together the second gates in one of the columns of the second memory cells;

a plurality of fifth lines each electrically connecting together the second source regions in one of the rows of the second memory cells;

a plurality of sixth lines each electrically connecting together the second drain regions in one of the columns of the second memory cells;

wherein the second plurality of synapses is configured to receive the second plurality of inputs as electrical voltages on the plurality of fourth lines, and to provide the second plurality of outputs as electrical currents on the plurality of fifth lines.

27. The neural network device of claim 26, wherein for each of the plurality of second memory cells, the second gate includes a second portion that extends up and over the second floating gate.

28. The neural network device of claim 26, further comprising:

a second plurality of neurons configured to receive the second plurality of outputs.