Silicon die with integrated high voltage devices

• US 10,700,039 B2
• Filed: 06/16/2014
• Issued: 06/30/2020
• Est. Priority Date: 06/16/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nelson, Donald W., Webb, M. Clair, Morrow, Patrick, Jun, Kimin
• Primary Examiner(s): Sefer, Ahmed N
• Application Number:
  US15/122,382
• Publication Number:
  US 20170069597A1
• Time in Patent Office: 2,206 Days
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0922 : Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

Claims

1. A method comprising:

forming a plurality of first devices on a substrate;

forming a plurality of first interconnects on the substrate wherein ones of the plurality of first interconnects are coupled to ones of the plurality of first devices;

coupling a second substrate to ones of the plurality of first interconnects;

subsequent to coupling the second substrate to the ones of the plurality of first interconnects coupled to the ones of the plurality of first devices, forming a plurality of second devices on the second substrate to form a second device layer, wherein the second device layer is electrically coupled to ones of the plurality of first interconnects;

forming a plurality of second interconnects on the second device layer wherein ones of the plurality of second interconnects are coupled to ones of the plurality of second devices; and

forming contact points to ones of the plurality of first interconnects, the contact points operable for connection to an external source.

2. The method of claim 1, wherein one of the plurality of first devices and the plurality of second devices comprise devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

3. The method of claim 1, wherein the substrate comprises a sacrificial substrate, the method further comprising:

coupling the sacrificial substrate to a carrier substrate; and

removing the sacrificial substrate.

4. The method of claim 3, wherein the plurality of the second devices comprise devices disposed at a finer pitch than a pitch of the plurality of first devices and coupling the sacrificial substrate to the carrier substrate comprises disposing the plurality of second interconnects between the device layer and the carrier substrate.

5. The method of claim 1, wherein forming a plurality of second interconnects comprises forming an interconnect stack comprising the plurality of second interconnects and a plurality of memory devices.

6. The method of claim 1, wherein one of the plurality of first devices comprise devices and the plurality of second devices are disposed at a finer pitch than a pitch of the other plurality of first devices and the plurality of second devices and one of the plurality of first devices and the plurality of second devices comprise devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

7. The method of claim 6, wherein forming a plurality of second devices comprises coupling the second devices to at least one of the plurality of first interconnects.

8. The method of claim 6, wherein coupling a device layer to ones of the plurality of first interconnects on the substrate comprises forming the plurality of second devices in a device layer on a second substrate and, after coupling the device layer to ones of the plurality of first interconnects, the method comprises thinning the second substrate.

9. A method comprising:

forming a first device layer comprising a plurality of first devices;

forming a plurality of first interconnects wherein ones of the plurality of first interconnects are coupled to ones of the plurality of first devices;

juxtaposing a second substrate to ones of the plurality of first interconnects;

subsequent to juxtaposing the second substrate to the ones of the plurality of first interconnects coupled to the ones of the plurality of first devices, forming a plurality of second devices on the second substrate to form a second device layer, wherein the second device layer is electrically coupled to ones of the plurality of first interconnects;

forming a plurality of second interconnects on the second device layer wherein ones of the plurality of second interconnects are coupled to ones of the plurality of second devices; and

juxtaposing contact points to ones of the plurality of first interconnects, the contact points operable for connection to an external source,

wherein one of the plurality of first devices and the plurality of second devices comprise devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

10. The method of claim 9, wherein the first device layer is formed on a sacrificial substrate, the method further comprising:

coupling the sacrificial substrate to a carrier substrate; and

removing the sacrificial substrate.

11. The method of claim 10, wherein the plurality of the second devices comprise devices disposed at a finer pitch than a pitch of the plurality of first devices and coupling the sacrificial substrate to the carrier substrate comprises disposing the plurality of second interconnects between the device layer and the carrier substrate.

12. The method of claim 9, wherein forming a plurality of second interconnects comprises forming an interconnect stack comprising the plurality of second interconnects and a plurality of memory devices.

13. The method of claim 9, wherein juxtaposing a second device layer to ones of the plurality of first interconnects comprises forming the plurality of second devices in a device layer on a substrate and, after juxtaposing the second device layer to ones of the plurality of first interconnects, the method comprises thinning the second substrate.