Gate drivers for stacked transistor amplifiers

• US 10,700,642 B2
• Filed: 01/04/2019
• Issued: 06/30/2020
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Wagh, Poojan, Pal, Kashish, Englekirk, Robert Mark, Ranta, Tero Tapio, Bargroff, Keith, Willard, Simon Edward
• Primary Examiner(s): Choe, Henry
• Application Number:
  US16/240,601
• Publication Number:
  US 20190158029A1
• Time in Patent Office: 543 Days
• Field of Search: 330311, 330310
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/21 Bias resistors are added at the input of an amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/522 the bias or supply voltage or current of the gate side of a FET amplifier being controlled to be on or off by a switch
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Claims

1. A method for biasing a transistor stack, the method comprising:

during a first mode of operation of the transistor stack, coupling gates of transistors of the stack, except an input transistor of the transistor stack, to low impedance nodes;

during a second mode of operation of the transistor stack, coupling said gates to high impedance nodes; and

based on the coupling during the first mode and the coupling during the second mode, providing a biasing voltage to each of said gates that is substantially same during both the first and second modes of operation, thereby obtaining a substantially same voltage distribution of a voltage across the transistor stack during said first and second modes of operation.

2. The method according to claim 1, wherein:

the second mode of operation is a standby mode, and

the high impedance nodes are provided via nodes of a first resistive ladder network whose series connected resistors have resistance values to provide a current flow through the first resistive ladder network that is as small as 3 μ

A.

3. The method according to claim 2, wherein:

the first mode of operation is an active mode,

the low impedance nodes are provided via output nodes of impedance converter elements, input nodes of the impedance converter elements coupled to the high impedance nodes, and

the impedance converter elements are configured to convert impedances of the high impedance nodes to lower impedances while passing voltages at respective input nodes to respective output nodes substantially unchanged.

4. The method according to claim 3, wherein the impedance converter elements comprise one or more of:

a) a transistor, and b) an operational amplifier.

5. The method according to claim 2, wherein:

the first mode of operation is an active mode,

the low impedance nodes are provided via nodes of a second resistive ladder network whose series connected resistors have resistance values according to desired impedance values of the low impedance nodes, and

voltages at nodes of the first resistive ladder network are substantially same as voltages at nodes of the second resistive ladder network.

6. The method according to claim 2, wherein:

the transistor stack comprises one or more gate capacitors each connected between a gate of a transistor of the transistor stack, except an input transistor of the transistor stack, and a reference voltage.

7. The method according to claim 6, wherein each said one more gate capacitor is configured to allow a gate voltage at the gate of the transistor to vary along with a radio frequency (RF) voltage at a drain of the transistor.

8. The method according to claim 7, wherein the one or more gate capacitors are configured to substantially equalize an output RF voltage at a drain of an output transistor of the transistor stack across a plurality of transistors of the transistor stack.

9. A circuital arrangement comprising:

a transistor stack configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor and an output transistor; and

a biasing circuit coupled to one or more gates of the plurality of stacked transistors via respective one or more switches,

wherein the circuital arrangement is configured to operate in at least a first mode and a second mode of operation,

wherein during the first mode of operation, the one or more switches couple the one or more gates to low impedance nodes of the biasing circuit to provide respective biasing voltages, and

wherein during the second mode of operation, the one or more switches couple the one or more gates to high impedance nodes of the biasing circuit to provide respective biasing voltages that are substantially same as the respective biasing voltages provided during the first mode of operation.

10. The circuital arrangement according to claim 9, wherein:

the second mode of operation is a standby mode, and

the biasing circuit comprises a first resistive ladder network that provides the high impedance nodes, the first resistive ladder network comprising series connected resistors having resistance values according to a desired current flow through the first resistive ladder network.

11. The circuital arrangement according to claim 10, wherein:

the first mode of operation is an active mode,

the biasing circuit further comprises impedance converter elements,

the low impedance nodes are provided via output nodes of the impedance converter elements, with input nodes of the impedance converter elements coupled to the high impedance nodes, and

the impedance converter elements are configured to convert impedances of the high impedance nodes to lower impedances while passing voltages at respective input nodes to respective output nodes substantially unchanged.

12. The circuital arrangement according to claim 11, wherein the impedance converter elements comprise one or more of:

a) a transistor, and b) an operational amplifier.

13. The circuital arrangement according to claim 10, wherein:

the first mode of operation is an active mode,

the biasing circuit comprises a second resistive ladder network that provides the low impedance nodes, the second resistive ladder network comprising series connected resistors having resistance values according to desired impedance values of the low impedance nodes, and

voltages at nodes of the first resistive ladder network are substantially same as voltages at nodes of the second resistive ladder network.

14. The circuital arrangement according to claim 10, wherein:

the transistor stack comprises one or more gate capacitors each connected between a gate of a transistor of the transistor stack except an input transistor of the transistor stack, and a reference voltage.

15. The circuital arrangement according to claim 14, wherein each said one or more gate capacitor is configured to allow a gate voltage at the gate of the transistor to vary along with a radio frequency (RF) voltage at a drain of the transistor.

16. The circuital arrangement according to claim 15, wherein the one or more gate capacitors are configured to substantially equalize an output RF voltage at a drain of an output transistor of the transistor stack across a plurality of transistors of the transistor stack.

17. The circuital arrangement according to claim 9, wherein the circuital arrangement is monolithically integrated using a fabrication technology comprising one of:

a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

18. An electronic module comprising the circuital arrangement of claim 9.