Enabling a non-core domain to control memory bandwidth in a processor

• US 10,705,588 B2
• Filed: 01/16/2019
• Issued: 07/07/2020
• Est. Priority Date: 10/27/2011
• Status: Active Grant

• Current Assignee: Daedalus Prime LLC (Daedalus Group LLC)
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Sodhi, Inder M., Rotem, Efraim, Rajwan, Doron, Weissmann, Eliezer, Wells, Ryan
• Primary Examiner(s): Phan, Raymond N
• Application Number:
  US16/249,103
• Publication Number:
  US 20190212801A1
• Time in Patent Office: 538 Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a plurality of cores including a first core operable at a first voltage and at a first frequency, and a second core operable at a second voltage independent of the first voltage and at a second frequency different from the first frequency;

graphics processing circuitry coupled to the plurality of cores to perform graphics operations, the graphics processing circuitry independently operable at a third frequency different from the first frequency and the second frequency; and

an interconnect to couple the graphics processing circuitry to a memory device, the interconnect operable at a fourth frequency different from the first, second, and third frequencies.

2. The processor of claim 1, further comprising:

first power management circuitry and/or logic to cause the first core to operate at the first frequency and to cause the second core to independently operate at the second frequency.

3. The processor of claim 1, further comprising:

a non-core power domain comprising a cache shared by the plurality of cores.

4. The processor of claim 2, further comprising:

second power management circuitry and/or logic to cause the graphics processing circuitry to operate at the third frequency.

5. The processor of claim 4, wherein the second power management circuitry and/or logic includes a mapping of selectable frequencies of the graphics processing circuitry to selectable frequencies of the interconnect.

6. The processor of claim 5, wherein the second power management circuitry and/or logic is to select the fourth frequency for the interconnect based on detecting operation of the graphics processing circuitry at the third frequency.

7. The processor of claim 3, further comprising:

power management circuitry and/or logic to cause the non-core power domain to operate at a different frequency from the first and second frequencies of the first and second cores, respectively.

8. A system comprising:

a system memory;

a plurality of cores coupled to the system memory;

a first core of the plurality of cores operable at a first voltage and at a first frequency, and a second core of the plurality of cores operable at a second voltage independent of the first voltage and at a second frequency different from the first frequency;

graphics processing circuitry coupled to the plurality of cores to perform graphics operations, the graphics processing circuitry independently operable at a third frequency different from the first frequency and the second frequency; and

an interconnect to couple the graphics processing circuitry to the system memory, the interconnect operable at a fourth frequency different from at least the first and second frequencies.

9. The system of claim 8, further comprising:

first power management circuitry and/or logic to cause the first core to operate at the first frequency and to cause the second core to independently operate at the second frequency.

10. The system of claim 8, further comprising:

a non-core power domain comprising a cache shared by the plurality of cores.

11. The system of claim 9, further comprising:

second power management circuitry and/or logic to cause the graphics processing circuitry to operate at the third frequency.

12. The system of claim 11, wherein the second power management circuitry and/or logic includes a mapping of selectable frequencies of the graphics processing circuitry to selectable frequencies of the interconnect.

13. The system of claim 12, wherein the second power management circuitry and/or logic is to select the fourth frequency for the interconnect based on detecting operation of the graphics processing circuitry at the third frequency.

14. The system of claim 10, further comprising:

power management circuitry and/or logic to cause the non-core power domain to operate at a different frequency from the first and second frequencies of the first and second cores, respectively.

15. The system of claim 8, further comprising:

a chipset coupled to the plurality of cores, the chip set comprising a plurality of interfaces to couple the cores to a plurality of I/O devices.

16. The system of claim 15, wherein one of the I/O devices comprises an audio generation device.

17. The system of claim 16, wherein one of the I/O devices comprises a video rendering device.

18. The system of claim 17, wherein one of the I/O devices comprises a user input device.

19. The system of claim 18, wherein one of the I/O devices comprises a network communication device.

20. An apparatus comprising:

means for operating a first core at a first voltage and at a first frequency while concurrently operating a second core at a second voltage independent of the first voltage and at a second frequency different from the first frequency;

means for independently operating a graphics processor at a third frequency different from the first frequency and the second frequency; and

interconnect means to couple the graphics processor to a memory device, the interconnect means operable at a fourth frequency different from the first, second, and third frequencies.