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Enabling a non-core domain to control memory bandwidth in a processor

DC
  • US 10,705,588 B2
  • Filed: 01/16/2019
  • Issued: 07/07/2020
  • Est. Priority Date: 10/27/2011
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a plurality of cores including a first core operable at a first voltage and at a first frequency, and a second core operable at a second voltage independent of the first voltage and at a second frequency different from the first frequency;

    graphics processing circuitry coupled to the plurality of cores to perform graphics operations, the graphics processing circuitry independently operable at a third frequency different from the first frequency and the second frequency; and

    an interconnect to couple the graphics processing circuitry to a memory device, the interconnect operable at a fourth frequency different from the first, second, and third frequencies.

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