Flash memory system

• US 10,705,736 B2
• Filed: 04/18/2019
• Issued: 07/07/2020
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Thammovong, Prasith
• Application Number:
  US16/387,875
• Publication Number:
  US 20190303004A1
• Time in Patent Office: 446 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

Claims

1. A configurable non-volatile memory device that supports a plurality of storage mode configurations, the memory device comprising:

a plurality of memory blocks, each memory block comprising a plurality of physical wordlines, each physical wordline configured to store a maximum of N logical pages, N being an integer greater than two,

the plurality of storage mode configurations comprising;

a N-bit-per-cell storage mode for programming all of the N logical pages for each physical wordline;

a two-bit-per-cell storage mode for programming two logical pages for each physical wordline; and

a single-bit-per-cell storage mode for programming a single logical page for each physical wordline; and

a plurality of I/O ports for receiving a program command packet, the program command packet comprising a row address and a write data to be programmed, the row address having at least one bit representing a selected physical wordline and at least one bit representing a logical page address of a subset of logical page addresses corresponding to the selected physical wordline when the configurable non-volatile memory device is operating in either of the N-bit-per-cell storage mode and the two-bit-per-cell storage mode.

2. The configurable non-volatile memory device of claim 1, wherein the two logical pages are the two lowest logical pages of the physical wordline.

3. The configurable non-volatile memory device of claim 1, wherein the single logical page is the lowest logical page of the physical wordline.

4. The configurable non-volatile memory device of claim 1, wherein the program command packet comprises N logical page addresses and corresponding N write data when the N-bit-per-cell storage mode is selected.

5. The configurable non-volatile memory device of claim 1, wherein the program command packet comprises two logical page addresses and corresponding two write data when the two-bit-per-cell storage mode is selected.

6. The configurable non-volatile memory device of claim 1, wherein the write data includes a meta-data indicating which storage mode configuration is selected.

7. The configurable non-volatile memory device of claim 1, wherein the write data includes a meta-data indicating a number of program/erase cycles performed on the memory block.