Program verify adaptation for flash memory

• US 10,705,900 B2
• Filed: 04/11/2018
• Issued: 07/07/2020
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Jin, Ming
• Primary Examiner(s): Lin, Katherine
• Application Number:
  US15/951,097
• Publication Number:
  US 20190243699A1
• Time in Patent Office: 818 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

Disclosed is a system and method for providing program verify adaptation for flash memory. The method includes performing an adjustment iteration, which includes accessing error counts for respective N states of a plurality of memory cells, applying a weighting to the error counts based on a binary data coding for the N states, determining a state Smin of the N states having a minimum error count Emin from the error counts, determining a state Smax of the N states having a maximum error count Emax from the error counts, determining a difference between the Emax and the Emin satisfies an error count threshold, and adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states, wherein the adjusting is a decrement when Smin is less than Smax and an increment otherwise.

Claims

1. A method for adapting program verify offsets for a memory of a solid state drive (SSD), the method comprising:

programming the memory by a controller of the SSD, wherein the controller is coupled to the memory, wherein the memory comprises one or more dies, wherein each of the one or more dies comprises blocks, wherein each of the blocks comprises wordlines, wherein each of the wordlines comprises memory cells, wherein the programming programs a plurality of memory cells within the one or more dies into N states, wherein each of the N states of the plurality of memory cells is associated with a program verify voltage;

performing, by the controller, an adjustment iteration on the one or more dies, wherein performing the adjustment iteration includes incrementing or decrementing the program verify offsets in an iterative manner to distribute errors across pages stored in the memory, wherein performing the adjustment iteration improves bit error correction and the SSD'"'"'s reliability over not performing the adjustment iteration, and wherein performing the adjustment iteration comprises;

accessing, by the controller, error counts for the respective N states of the plurality of memory cells within the one or more dies, wherein the error counts are for errors between the respective N states and adjacent lower states;

applying, by the controller, a weighting to the error counts, wherein the weighting is based on a binary data coding for the N states;

determining, by the controller, a state Smin of the N states having a minimum error count Emin from the error counts;

determining, by the controller, a state Smax of the N states having a maximum error count Emax from the error counts;

determining, by the controller, a difference between the Emax and the Emin satisfies an error count threshold; and

adjusting using the controller, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states,

wherein the predefined value is a voltage increment recognizable by a digital-to-analog converter circuit for performing reads on one or more memory cells within the one or more dies,

wherein the adjusting is a decrement when Smin is less than Smax, and

wherein the adjusting is an increment when Smin is greater than Smax;

storing, by the controller, the adjusted program verify offsets into registers; and

programming, by the controller, at least some of the wordlines using the adjusted program verify offsets.

2. The method of claim 1, further comprising, prior to performing the adjustment iteration:

determining an adaptation is due for adjusting the program verify offsets for the N states programmable into the plurality of memory cells.

3. The method of claim 2, wherein determining the adaptation is due is by a program/erase (P/E) cycle count for the plurality of memory cells reaching a periodic threshold value.

4. The method of claim 1, further comprising:

repeating the performing of the adjustment iteration until the difference between the Emax and the Emin does not satisfy the error count threshold, wherein a minimum number of read operations on data programmed with the adjusted program verify offsets is met after each repeating.

5. The method of claim 1, further comprising:

incrementing the program verify offset of a highest program state of the N states.

6. The method of claim 1, wherein the error counts are sampled from a representative distribution of the plurality of memory cells.

7. A solid state drive for facilitating adaption of program verify offsets for a plurality of memory cells, the solid state drive comprising:

a plurality of memory devices comprising one or more dies, wherein each of the one or more dies comprises blocks, wherein each of the blocks comprises wordlines, wherein each of the wordlines comprises memory cells; and

a controller configured to;

program the plurality of memory cells within the one or more dies into N states, wherein each of the N states of the plurality of memory cells is associated with a program verify voltage;

perform an adjustment iteration on the one or more dies, wherein performing the adjustment iteration includes incrementing or decrementing the program verify offsets in an iterative manner to distribute errors across pages stored in the plurality of memory devices, wherein performing the adjustment iteration facilitates improvement of bit error correction and the solid state drive'"'"'s reliability over not performing the adjustment iteration, and wherein performing the adjustment iteration comprises;

accessing error counts for respective N states of the plurality of memory cells in a memory device of the plurality of memory devices, wherein the error counts are for errors between the respective N states and adjacent lower states;

applying a weighting to the error counts, wherein the weighting is based on a binary data coding for the N states;

determining a state Smin of the N states having a minimum error count Emin from the error counts;

determining a state Smax of the N states having a maximum error count Emax from the error counts;

determining a difference between the Emax and the Emin satisfies an error count threshold; and

adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states,

wherein the predefined value is a voltage increment recognizable by a digital-to-analog converter circuit for performing reads on one or more memory cells in the memory device of the plurality of memory devices,

wherein the adjusting is a decrement when Smin is less than Smax, and

wherein the adjusting is an increment when Smin is greater than Smax;

repeat the performing of the adjustment iteration until the difference between the Emax and the Emin does not satisfy the error count threshold, wherein a minimum number of read operations on data programmed with the adjusted program verify offsets is met after each repeating;

store the adjusted program verify offsets into registers; and

program at least some of the wordlines using the adjusted program verify offsets.

8. The solid state drive of claim 7, wherein the controller is further configured to:

determine, prior to performing the adjustment iteration, that an adaptation is due for adjusting the program verify offsets for the N states programmable into the plurality of memory cells.

9. The solid state drive of claim 8, wherein the controller is configured to determine that the adaptation is due when a program/erase (P/E) cycle count for the plurality of memory cells reaches a periodic threshold value.

10. The solid state drive of claim 7, wherein the controller is further configured to:

increment the program verify offset of a highest program state of the N states.

11. The solid state drive of claim 7, wherein the controller is configured to sample the error counts from a representative distribution of the plurality of memory cells.

12. A non-transitory machine-readable medium including machine-executable instructions thereon that, when executed by a processor, perform a method for adapting a plurality of program verify offsets for a memory of a solid state drive (SSD), wherein the method comprises:

programming the memory by the processor, wherein the processor is coupled to the memory, wherein the memory comprises one or more dies, wherein each of the one or more dies comprises blocks, wherein each of the blocks comprises wordlines, wherein each of the wordlines comprises memory cells, wherein the programming programs a plurality of memory cells within the one or more dies into N states, wherein each of the N states of the plurality of memory cells is associated with a program verify voltage;

determining, by the processor, an adaptation is due for adjusting program verify offsets for the N states of the plurality of memory cells, wherein the determining is by a program/erase (P/E) cycle count for the plurality of memory cells reaching a periodic threshold value; and

performing, by the processor, an adjustment iteration on the one or more dies, wherein performing the adjustment iteration includes incrementing or decrementing the program verify offsets in an iterative manner to distribute errors across pages stored in the memory, wherein performing the adjustment iteration improves bit error correction and the SSD'"'"'s reliability over not performing the adjustment iteration, and wherein performing the adjustment iteration comprises;

accessing, by the processor, error counts for the respective N states of the plurality of memory cells within the one or more dies, wherein the error counts are for errors between the respective N states and adjacent lower states;

applying, by the processor, a weighting to the error counts, wherein the weighting is based on a binary data coding for the N states;

determining, by the processor, a state Smin of the N states having a minimum error count Emin from the error counts;

determining, by the processor, a state Smax of the N states having a maximum error count Emax from the error counts;

determining, by the processor, a difference between the Emax and the Emin satisfies an error count threshold; and

adjusting using the processor, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states,

wherein the predefined value is a voltage increment recognizable by a digital-to-analog converter circuit for performing reads on one or more memory cells within the one or more dies,

wherein the adjusting is a decrement when Smin is less than Smax, and

wherein the adjusting is an increment when Smin is greater than Smax;

storing, by the processor, the adjusted program verify offsets into registers; and

programming, by the processor, at least some of the wordlines using the adjusted program verify offsets.

13. The non-transitory machine-readable medium of claim 12, wherein the method further comprises:

repeating the performing of the adjustment iteration until the difference between the Emax and the Emin does not satisfy the error count threshold, wherein a threshold number of read operations on data programmed with the adjusted program verify offsets is met after each repeating.

14. The non-transitory machine-readable medium of claim 12, wherein the method further comprises:

incrementing the program verify offset of a highest program state of the N states.

15. The non-transitory machine-readable medium of claim 12, wherein the error counts are sampled from a representative distribution of the plurality of memory cells.

16. A system for facilitating adaption of program verify offsets for a memory, the system comprising:

means for programming the memory, wherein the memory comprises one or more dies, wherein each of the one or more dies comprises blocks, wherein each of the blocks comprises wordlines, wherein each of the wordlines comprises memory cells, wherein the programming programs a plurality of memory cells within the one or more dies into N states, wherein each of the N states of the plurality of memory cells is associated with a program verify voltage;

means for performing an adjustment iteration, wherein the means for performing the adjustment iteration includes means for incrementing or decrementing the program verify offsets in an iterative manner to distribute errors across pages stored in the memory, wherein the means for performing the adjustment iteration facilitates improvement of bit error correction and the system'"'"'s reliability over not performing the adjustment iteration, and wherein the means for performing the adjustment iteration comprises;

means for accessing error counts for the respective N states of the plurality of memory cells within the one or more dies, wherein the error counts are for errors between the respective N states and adjacent lower states;

means for applying a weighting to the error counts, wherein the weighting is based on a binary data coding for the N states;

means for determining a state Smin of the N states having a minimum error count Emin from the error counts;

means for determining a state Smax of the N states having a maximum error count Emax from the error counts;

means for determining a difference between the Emax and the Emin satisfies an error count threshold; and

means for adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states,

wherein the predefined value is a voltage increment recognizable by a digital-to-analog converter circuit for performing reads on one or more memory cells within the one or more dies,

wherein the adjusting is a decrement when Smin is less than Smax, and

wherein the adjusting is an increment when Smin is greater than Smax;

means for repeating the performing of the adjustment iteration until the difference between the Emax and the Emin does not satisfy the error count threshold, wherein a threshold number of read operations on data programmed with the adjusted program verify offsets is met after each repeating;

means for storing the adjusted program verify offsets into registers; and

means for programming at least some of the wordlines using the adjusted program verify offsets.

17. The system of claim 16, further comprising:

means for determining an adaptation is due for adjusting the program verify offsets for the N states programmable into the plurality of memory cells.

18. The system of claim 17, wherein determining the adaptation is due is by a program/erase (P/E) cycle count for the plurality of memory cells reaching a periodic threshold value.

19. The system of claim 16, further comprising:

means for incrementing the program verify offset of a highest program state of the N states.

20. The system of claim 16, wherein the error counts are sampled from a representative distribution of the plurality of memory cells.