Memory controller

• US 10,706,910 B2
• Filed: 02/25/2019
• Issued: 07/07/2020
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US16/284,375
• Publication Number:
  US 20190325936A1
• Time in Patent Office: 498 Days
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Claims

1. A memory controller component comprising:

a clock driver to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having read-data transmit circuitry to output read data at transmit times dependent on transitions of the first clock signal and write-data receive circuitry to sample write data at sampling times dependent on transitions of the first clock signal;

a write-data transmitter to transmit the write data to the DRAM in response to transitions of a second clock signal;

a read-data receiver to sample the read data transmitted by the DRAM in response to transitions of a third clock signal; and

clocking circuitry to generate the second and third clock signals in response to transitions of the first clock signal, the clocking circuitry including phase control circuitry to independently offset phases of the second and third clock signals relative to the first clock signal.

2. The memory controller component of claim 1 wherein the phase control circuitry to independently offset phases of the second and third clock signals relative to the first clock signal comprises first phase control circuitry to offset the phase of the second clock signal relative to the first clock signal such that the write data transmitted by the write-data transmitter in response to the transitions of the second clock signal arrives at the write-data receive circuitry of the DRAM in a desired phase relation with the sampling times.

3. The memory controller component of claim 2 wherein the phase control circuitry to independently offset phases of the second and third clock signals relative to the first clock signal comprises second phase control circuitry to offset the phase of the third clock signal relative to the first clock signal such that the third clock signal is aligned, within the read-data receiver, with the read data transmitted by the DRAM.

4. The memory controller component of claim 2 wherein the first phase control circuitry comprises circuitry to offset the phase of the second clock signal relative to the first clock signal in accordance with a digital control value that specifies a phase offset between the second clock signal and the first clock signal.

5. The memory controller component of claim 2 wherein the first phase control circuitry comprises (i) clock phase inputs to receive a plurality of clock phases having respective phase offsets relative to a transition of the first clock signal and (ii) circuitry to synthesize the second clock signal from the plurality of clock phases.

6. The memory control component of claim 5 wherein the circuitry to synthesize the second clock signal from the plurality of clock phases comprises phase-select circuitry to select a first clock phase and a second clock phase from among the plurality of clock phases and interpolation circuitry to interpolate between the first and second clock phases to produce the second clock signal.

7. The memory control component of claim 6 wherein the first phase control circuitry further comprises an input to receive a digital phase control value, and wherein the phase-select circuitry selects the first and second clock phases based on the digital phase control value and wherein the interpolation circuitry interpolates between the first and second clock phases based on the digital phase control value.

8. The memory control component of claim 7 wherein the first phase control circuitry to offset the phase of the second clock signal relative to the first clock signal comprises circuitry to adjust the digital control value.

9. The memory control component of claim 1 wherein the write-data transmitter to transmit the write data to the DRAM in response to transitions of the second clock signal comprises circuitry to transmit first and second portions of the write data to the DRAM during respective half-cycles of the second clock cycle.

10. The memory control component of claim 1 wherein the phase control circuitry to independently offset phases of the second and third clock signals relative to the first clock signal comprises calibration circuitry to adjust the phase of the second clock signal in a calibration operation that includes transmitting test data to the DRAM via the write-data transmitter and reading back the test data from the DRAM via the read-data receiver.

11. A method of operation within a memory controller component, the method comprising:

outputting a first clock signal to a dynamic random access memory device (DRAM), the DRAM having read-data transmit circuitry to output read data at transmit times dependent on transitions of the first clock signal and write-data receive circuitry to sample write data at sampling times dependent on transitions of the first clock signal;

transmitting write data to the DRAM in response to transitions of a second clock signal;

sampling read data transmitted by the DRAM in response to transitions of a third clock signal; and

generating the second and third clock signals in response to transitions of the first clock signal, including independently offsetting phases of the second and third clock signals relative to the first clock signal.

12. The method of claim 11 wherein independently offsetting phases of the second and third clock signals relative to the first clock signal comprises offsetting the phase of the second clock signal relative to the first clock signal such that the write data transmitted in response to the transitions of the second clock signal arrives at the write-data receive circuitry of the DRAM in a desired phase relation with the sampling times.

13. The method of claim 12 wherein independently offsetting phases of the second and third clock signals relative to the first clock signal comprises offsetting the phase of the third clock signal relative to the first clock signal such that the third clock signal is aligned, within the memory controller component, with the read data transmitted by the DRAM.

14. The memory controller component of claim 12 wherein offsetting the phase of the second clock signal relative to the first clock signal such that the write data transmitted in response to the transitions of the second clock signal arrives at the write-data receive circuitry of the DRAM in a desired phase relation with the sampling times comprises adjusting the phase of the second clock signal in accordance with a digital control value that indicates a phase offset between the second clock signal and the first clock signal.

15. The method of claim 12 wherein offsetting the phase of the second clock signal relative to the first clock signal comprises receiving a plurality of clock phases having respective phase offsets relative to a transition of the first clock signal and synthesizing the second clock signal from the plurality of clock phases.

16. The method of claim 15 wherein synthesizing the second clock signal from the plurality of clock phases comprises selecting a first clock phase and a second clock phase from among the plurality of clock phases and interpolating between the first and second clock phases to produce the second clock signal.

17. The method of claim 16 wherein selecting the first and second clock phases from among the plurality of clock phases comprises selecting the first and second clock phases based on the digital phase control value and wherein the interpolating between the first and second clock phases to produce the second clock signal comprises interpolating between the first and second clock phases based on the digital phase control value.

18. The method of claim 17 wherein offsetting the phase of the second clock signal relative to the first clock signal comprises adjusting the digital control value.

19. The method of claim 11 wherein independently offsetting phases of the second and third clock signals relative to the first clock signal comprises adjusting the phase of the second clock signal in a calibration operation that includes transmitting test data to the DRAM via the write-data transmitter and reading back the test data from the DRAM via the read-data receiver.

20. A memory controller component comprising:

means for outputting a first clock signal to a dynamic random access memory device (DRAM), the DRAM having read-data transmit circuitry to output read data at transmit times dependent on transitions of the first clock signal and write-data receive circuitry to sample write data at sampling times dependent on transitions of the first clock signal;

means for transmitting write data to the DRAM in response to transitions of a second clock signal;

means for sampling read data transmitted by the DRAM in response to transitions of a third clock signal; and

means for generating the second and third clock signals in response to transitions of the first clock signal, including means for independently offsetting phases of the second and third clock signals relative to the first clock signal.