Method and apparatus for integrated level-shifter and memory clock
First Claim
Patent Images
1. A level-shifting circuit configured to provide a CLKI signal in a high voltage domain in response to a CLK signal in a low voltage domain, comprising:
- a first NFET having a gate coupled to the CLK signal in the low voltage domain, a drain coupled to a NCLK_N node, and a source coupled to a first intermediate node;
a second NFET having a drain coupled to the first intermediate node, a source coupled to ground, and a gate coupled to an ENCLK_T node;
a first PFET having a gate coupled to the CLK signal, a drain coupled to the NCLK_N node, and a source coupled to a second intermediate node;
a second PFET having a drain coupled to the second intermediate node, a source coupled to a high voltage source in the high voltage domain, and a gate coupled to the CLKI signal;
a third NFET having a drain coupled to the NCLK_N node, a source coupled to the first intermediate node, and a gate coupled to the CLKI signal;
a first inverter having an input coupled to the NCLK_N node and an output coupled to the CLKI signal;
a third PFET having a source coupled to the high voltage source in the high voltage domain, a gate coupled to the ENCLK_T node, and a drain coupled to the NCLK_N node;
a second inverter in a low power domain having an input coupled to the CLK signal and an output coupled to a third intermediate node;
a first nor gate having a first input coupled to the third intermediate node, a second input coupled to the ENCLK_T node, and an output coupled to a fourth intermediate node; and
a second nor gate having a first input coupled to the fourth intermediate node;
a second input coupled to a MRST_P input signal, and an output coupled to the ENCLK_T node.
2 Assignments
0 Petitions
Accused Products
Abstract
An integrated level-shifter and memory clock is disclosed that minimizes delay of voltage level-shifting from an external clock on a first logic supply voltage to an internal clock on a higher array supply voltage that is pulse-width independent of the external clock used to generate the internal clock. The generation of the internal clock on the higher array supply voltages is accomplished in two stages of logic. An array-tracking timing delay circuit mimics access delay to generate a MRST_P to reset the internal clock on the higher array supply voltage.
38 Citations
18 Claims
-
1. A level-shifting circuit configured to provide a CLKI signal in a high voltage domain in response to a CLK signal in a low voltage domain, comprising:
-
a first NFET having a gate coupled to the CLK signal in the low voltage domain, a drain coupled to a NCLK_N node, and a source coupled to a first intermediate node; a second NFET having a drain coupled to the first intermediate node, a source coupled to ground, and a gate coupled to an ENCLK_T node; a first PFET having a gate coupled to the CLK signal, a drain coupled to the NCLK_N node, and a source coupled to a second intermediate node; a second PFET having a drain coupled to the second intermediate node, a source coupled to a high voltage source in the high voltage domain, and a gate coupled to the CLKI signal; a third NFET having a drain coupled to the NCLK_N node, a source coupled to the first intermediate node, and a gate coupled to the CLKI signal; a first inverter having an input coupled to the NCLK_N node and an output coupled to the CLKI signal; a third PFET having a source coupled to the high voltage source in the high voltage domain, a gate coupled to the ENCLK_T node, and a drain coupled to the NCLK_N node; a second inverter in a low power domain having an input coupled to the CLK signal and an output coupled to a third intermediate node; a first nor gate having a first input coupled to the third intermediate node, a second input coupled to the ENCLK_T node, and an output coupled to a fourth intermediate node; and a second nor gate having a first input coupled to the fourth intermediate node;
a second input coupled to a MRST_P input signal, and an output coupled to the ENCLK_T node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method of operating a memory clock level-shifter configured to generate a CLKI signal in a high voltage domain in response to a CLK signal in a low voltage domain comprising the steps:
-
configuring a first NFET having a gate coupled to the CLK signal in a low voltage domain, a drain coupled to a NCLK_N node, and a source coupled to a first intermediate node; configuring a second NFET having a drain coupled to the first intermediate node, a source coupled to ground, and a gate coupled to an ENCLK_T node; configuring a first PFET having a gate coupled to the CLK signal, a drain coupled to the NCLK_N node, and a source coupled to a second intermediate node; configuring a second PFET having a drain coupled to the second intermediate node, a source coupled to a high voltage source in the high voltage domain, and a gate coupled to the CLKI signal; configuring a third NFET having a drain coupled to the NCLK_N node, a source coupled to the first intermediate node, and a gate coupled to the CLKI signal; configuring a first inverter having an input coupled to the NCLK_N node and an output coupled to the CLKI signal; configuring a third PFET having a source coupled to the high voltage source in the high voltage domain, a gate coupled to the ENCLK_T node, and a drain coupled to the NCLK_N node; configuring a second inverter having an input coupled to the CLK signal and an output coupled to a third intermediate node; configuring a first nor gate having a first input coupled to the third intermediate node, a second input coupled to the ENCLK_T node, and an output coupled to a fourth intermediate node; and configuring a second nor gate having a first input coupled to the fourth intermediate node;
a second input coupled to a MRST_P input signal, and an output coupled to the ENCLK_T node. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
Specification