Non-volatile memory device, in particular phase change memory, and reading method

• US 10,706,924 B2
• Filed: 04/24/2019
• Issued: 07/07/2020
• Est. Priority Date: 05/04/2018
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Campardo, Giovanni, Annunziata, Roberto, Zuliani, Paola
• Primary Examiner(s): Le, Vu A
• Application Number:
  US16/393,115
• Publication Number:
  US 20190341103A1
• Time in Patent Office: 440 Days
• Field of Search: 365163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A non-volatile memory device has a circuit branch associated to a bit line connected to a memory cell. When the memory cell is read, in a precharging step, the bit line is precharged. In a characteristic shift step, the memory cell is activated, and a current source is activated to supply a shift current to the first bit line and cause the bit line to charge or discharge on the basis of the datum stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to an input of a comparator stage that compares the voltage on the bit line with a reference voltage to supply an output signal indicating a datum stored in the memory cell.

Claims

1. A non-volatile memory device, comprising:

a memory array formed by a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing a datum is arranged in a first column and is coupleable to a first bit line;

a first circuit branch associated to the first bit line and having;

a first node coupled to the first bit line;

an output node; and

switch means configured to selectively couple the first node to the first memory cell and the first bit line to the output node;

a comparator stage having a first input coupled to the output node, a second input coupled to a reference voltage, and an output supplying an output signal indicative of a datum stored in the first memory cell;

a current source, controllable to inject a shift current into the first bit line, the shift current having a value higher than a current passing in the first memory cell when the latter is in a first programming state, and lower than the current passing in the first memory cell when the latter is in a second programming state; and

a control unit configured to control, during reading of the first memory cell, the switch means so that;

in a precharging step, when the first memory cell is disabled, the first bit line is precharged at a line precharging voltage, and the current source is deactivated and does not supply the shift current;

in a characteristic shift step, when the first memory cell is enabled and connected to the bit line, the first bit line is decoupled from the output node, and the current source is activated and supplies the shift current to the first bit line, thereby the bit line charges or discharges on the basis of the datum stored; and

in a detection step, the current source is deactivated, and the switch means connects the first bit line to the output node.

2. The device according to claim 1, wherein the first circuit branch further comprises:

a second node;

a first connection switch configured to selectively couple the first node to the second node; and

a second connection switch configured to selectively couple the second node to the output node,

wherein, in the precharging step, the first and second nodes are precharged at respective precharging voltages;

in the characteristic shift step, the second connection switch decouples the second node from the output node; and

, in the detection step, the second connection switch connects the second node to the output node.

3. The device according to claim 2, further comprising a first capacitance coupled to the first node and a second capacitance coupled to the output node;

wherein the control unit is configured so that, in a sharing step, following the characteristic-shift step and prior to the detection step, the first memory cell is decoupled from the first node, the current source is deactivated, and the second node is coupled to the output node to cause a charge sharing between the first and second capacitances.

4. The device according to claim 2, wherein the memory array comprises a second memory cell storing a datum, the second memory cell being arranged in a second column and being coupleable to a second bit line, different from the first bit line, the device further comprising:

a second circuit branch associated to the second bit line and having a third node coupled to the second bit line;

a fourth node; and

a reference node, coupled to the second input of the comparator stage;

a third connection switch arranged between the third node and the fourth node;

a fourth connection switch arranged between the fourth node and the reference node; and

a coupling stage, comprising a first coupling switch, controllable by the control unit to couple the output node and the reference node in an equalization step following the precharging step and before the characteristic shift step, and to decouple the output node and the reference node in the characteristic shift and detection steps.

5. The device according to claim 4 when depending upon claim 3, wherein the coupling stage further comprises a second coupling switch controllable by the control unit to couple the second and fourth nodes of the first and second circuit branches during the equalization step, and to decouple the second and fourth nodes during the characteristic shift and sharing steps.

6. The device according to claim 5, wherein the coupling stage further comprises a third coupling switch, controllable by the control unit, to couple the first and third nodes of the first and second circuit branches during the equalization step, and decouple the first and third nodes during the characteristic shift and sharing steps.

7. The device according to claim 3, wherein the first bit line comprises a first global bit line and a first local bit line;

and the first circuit branch further comprises a fifth connection transistor having a first terminal coupled to the first local bit line, a second terminal coupled to the first global bit line, and a control terminal receiving a first local decoding signal from the control unit, wherein the fifth connection transistor is controllable by the control unit so as to couple the first local bit line to the first global bit line in the precharging, equalization, and characteristic shift steps, and decouple the first local bit line from the first global bit line in the sharing step.

8. The device according to claim 7 when depending upon claim 4, wherein the second bit line comprises a second global bit line and a second local bit line;

and the second circuit branch further comprises a sixth connection transistor having a first terminal coupled to the second local bit line, a second terminal coupled to the second global bit line, and a control terminal receiving a second local decoding signal from the control unit, wherein the sixth connection transistor is controllable by the control unit so as to keep the second memory cell off during reading of the first memory cell.

9. The device according to claim 8, wherein the first and second global bit lines are adjacent.

10. The device according to claim 1, wherein the memory cells are phase change memory cells.

11. The device according to any of claim 2, wherein the current source is selectively coupled to the second node.

12. A method for reading a memory cell of a non-volatile memory device having a memory array formed by a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing a datum is arranged in a first column and is coupleable to a first bit line;

a first circuit branch is associated to the first bit line and has a first node coupled to the first bit line, an output node, and a current source controllable to inject a shift current in the first bit line, the shift current having a value higher than a current passing the first memory cell when the first memory cell is in a first programming state, and lower than the current passing the first memory cell when the first memory cell is in a second programming state,

the method comprising;

a precharging step, wherein the first memory cell is disabled, the first bit line is precharged at a line precharging voltage, and the current source is deactivated and does not supply the shift current;

a characteristic shift step, wherein the first memory cell is enabled and connected to the first bit line, the first bit line is decoupled from the output node, and the current source supplies the shift current to the first bit line, and wherein, on the basis of the datum stored, the bit line goes to a shifted voltage, lower or higher than the precharging line voltage; and

a detection step, wherein the shift current is interrupted, the first bit line is connected to the output node, and the translated voltage is compared with a reference voltage.

13. The method according to claim 12, wherein the first circuit branch further comprises a second node interposed between the first node and the output node, wherein:

in the precharging step, the first and second nodes are precharged at respective first voltage values;

in the characteristic shift step, the second node is decoupled from the output node; and

in the detection step, the second node is coupled to the output node.

14. The method according to claim 13, wherein the shift current is a constant current.

15. The method according to claim 13, further comprising a sharing step following the characteristic shift step and before the detection step, wherein the first memory cell is decoupled from the first node, the current source is deactivated, and the first and second nodes are coupled together to generate a charge sharing between a first capacitance coupled to the first node and a second capacitance coupled to the second node.

16. The method according to claim 15, wherein, in the sharing step, the second voltage value on the first node is lower than the first voltage value on the first node, when the datum stored is a logic ‘

1’

; and

is higher than the first voltage value on the first node, when the datum stored is a logic ‘

0’

.

17. The method according to claim 13, wherein the memory array comprises a second memory cell storing a datum, arranged in a second column and coupleable to a second bit line, different from the first bit line, and the device further comprises a second circuit branch associated to the second bit line and having a third node coupled to the second bit line;

a fourth node selectively coupleable to the third node; and

a reference node selectively coupleable to the fourth node and coupled to the second input of the comparator stage to supply the reference voltage;

the method further comprising;

an equalization step following the precharging step and before the characteristic shift step, wherein the output node and the reference node are coupled together and brought to a same voltage value,

wherein, in the characteristic shift step, the output node and the reference node are decoupled from each other; and

during the detection step, voltages at the output node and on the reference node are compared.

18. The method according to claim 17, wherein, in the equalization step, the first node and the third node are coupled together and brought to a same voltage, and the second node and the fourth node are coupled together and brought to a same voltage.

19. A non-volatile memory device, comprising:

a memory array formed by a plurality of memory cells arranged in rows and columns, wherein at least one first memory cell storing a datum is arranged in a first column and is coupleable to a first bit line;

a first circuit branch associated to the first bit line and having;

a first node coupled to the first bit line;

an output node; and

a switch configured to selectively couple the first node to the first memory cell and the first bit line to the output node;

a comparator stage having a first input coupled to the output node, a second input coupled to a reference voltage, and an output supplying an output signal indicative of a datum stored in the first memory cell;

a current source, controllable to inject a shift current into the first bit line, the shift current having a value higher than a current passing in the first memory cell when the latter is in a first programming state, and lower than the current passing in the first memory cell when the latter is in a second programming state; and

a control unit configured to control the switch.

20. The non-volatile memory device, wherein the control unit is configured to provide a precharging mode of operation, a characteristic shift mode of operation, and a detection mode of operation.