Non-volatile static random access memory architecture having single non-volatile bit per volatile memory bit

• US 10,706,928 B2
• Filed: 07/24/2018
• Issued: 07/07/2020
• Est. Priority Date: 07/24/2018
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Tailliet, Francois, Battista, Marc
• Primary Examiner(s): Siddique, Mushfique
• Application Number:
  US16/043,425
• Publication Number:
  US 20200035303A1
• Time in Patent Office: 714 Days
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

Disclosed herein is a method of operating a non-volatile static random access NVSRAM memory formed from words. Each word includes NVSRAM cells, each of those NVSRAM cells having an SRAM cell and an electronically erasable programmable read only memory EEPROM cell. If the SRAM cells of a word have been accessed since powerup, data is read from the NVSRAM cells of that word through the SRAM cells. However, if the SRAM cells of that word have not been written since powerup, data is read from the NVSRAM cells of that word through the EEPROM cells.

Claims

1. A non-volatile static random access memory (NVSRAM), comprising:

a NVSRAM cell comprising;

a static random access memory (SRAM) memory cell;

a first gate selectively directly electrically coupling the SRAM memory cell to a bit line based upon a word level word line signal;

a buffer circuit transferring a logic state of the SRAM memory cell to the bit line based upon a SRAM read word line signal;

a singular electrically erasable programmable read only memory (EEPROM) memory cell having a control terminal receiving a control gate signal;

a second gate selectively directly electrically coupling the singular EEPROM memory cell to the bit line based upon an EEPROM read signal; and

a third gate selectively directly electrically coupling the SRAM memory cell to the singular EEPROM memory cell based upon a reload signal; and

a power source latch configured to generate a power source signal for powering the SRAM memory cell,

wherein the power source latch comprises;

a first latch configured to be set when a reset write signal is at a logic high and to be reset when both of a set signal and a word line for the SRAM memory cell are at a logic high; and

an inverter having an input coupled to an output of the first latch;

wherein the power source signal is generated at an output of the inverter.

2. The NVSRAM of claim 1, further comprising a control gate latch configured to generate the control gate signal, the control gate latch configured to be set when either both of an erase signal and the power source signal are at a logic high or when both of a program signal and a complement of the power source signal are at a logic high, the control gate latch configured to be reset when a read signal is at a logic high.

3. The NVSRAM of claim 2, wherein the EEPROM memory cell comprises a floating gate having a gate coupled to the control gate signal.

4. The NVSRAM of claim 1, wherein the singular EEPROM memory cell comprises a floating gate having a gate coupled to the control gate signal.

5. A non-volatile static random access memory (NVSRAM) of claim 2, comprising:

a NVSRAM cell comprising;

a static random access memory (SRAM) memory cell;

a first gate selectively directly electrically coupling the SRAM memory cell to a bit line based upon a word level word line signal;

a buffer circuit transferring a logic state of the SRAM memory cell to the bit line based upon a SRAM read word line signal;

a singular electrically erasable programmable read only memory (EEPROM) memory cell having a control terminal receiving a control gate signal;

a second gate selectively directly electrically coupling the singular EEPROM memory cell to the bit line based upon an EEPROM read signal; and

a third gate selectively directly electrically coupling the SRAM memory cell to the singular EEPROM memory cell based upon a reload signal; and

a power source latch configured to generate a power source signal for powering the SRAM memory cell,

wherein the power source latch comprises;

a first latch configured to be set when a reset write signal is at a logic high and to be reset when the word level word line signal is at a logic high; and

an inverter having an input coupled to an output of the first latch;

wherein the power source signal is generated at an output of the inverter.

6. A non-volatile static random access memory (NVSRAM) of claim 1, comprising:

a NVSRAM cell comprising;

a static random access memory (SRAM) memory cell;

a first gate selectively directly electrically coupling the SRAM memory cell to a bit line based upon a word level word line signal;

a buffer circuit transferring a logic state of the SRAM memory cell to the bit line based upon a SRAM read word line signal;

a singular electrically erasable programmable read only memory (EEPROM) memory cell having a control terminal receiving a control gate signal;

a second gate selectively directly electrically coupling the singular EEPROM memory cell to the bit line based upon an EEPROM read signal; and

a third gate selectively directly electrically coupling the SRAM memory cell to the singular EEPROM memory cell based upon a reload signal; and

control logic configured to generate the word level word line signal and a reset signal for selectively resetting the SRAM memory cell as a function of a word line signal for the SRAM memory cell and a signal indicating whether a power source signal for powering the SRAM memory cell is at a logic high.

7. A non-volatile static random access memory (NVSRAM), comprising:

a NVSRAM cell comprising;

a static random access memory (SRAM) memory cell;

a first gate selectively directly electrically coupling the SRAM memory cell to a bit line based upon a word level word line signal;

a buffer circuit transferring a logic state of the SRAM memory cell to the bit line based upon a SRAM read word line signal;

a singular electrically erasable programmable read only memory (EEPROM) memory cell having a control terminal receiving a control gate signal;

a second gate selectively directly electrically coupling the singular EEPROM memory cell to the bit line based upon an EEPROM read signal; and

a third gate selectively directly electrically coupling the SRAM memory cell to the singular EEPROM memory cell based upon a reload signal; and

wherein the SRAM memory cell comprises;

first and second inverters;

wherein an input of the first inverter is coupled to an output of the second inverter;

wherein an input of the second inverter is coupled to an output of the first inverter;

wherein the buffer circuit comprises;

a first buffering transistor having a drain coupled to the bit line, a source, and a gate coupled to a SRAM read word line; and

a second buffering transistor having a drain coupled to the source of the first buffering transistor, a source coupled to ground, and a gate coupled to the output of the first inverter; and

a reset transistor coupled between the output of the first inverter and ground.

8. A non-volatile static random access memory (NVSRAM), comprising:

a NVSRAM cell comprising;

a static random access memory (SRAM) memory cell;

a first gate selectively directly electrically coupling the SRAM memory cell to a bit line based upon a word level word line signal;

a buffer circuit transferring a logic state of the SRAM memory cell to the bit line based upon a SRAM read word line signal;

a singular electrically erasable programmable read only memory (EEPROM) memory cell having a control terminal receiving a control gate signal;

a second gate selectively directly electrically coupling the singular EEPROM memory cell to the bit line based upon an EEPROM read signal; and

a third gate selectively directly electrically coupling the SRAM memory cell to the singular EEPROM memory cell based upon a reload signal; and

wherein the SRAM memory cell comprises;

first and second inverters;

wherein an input of the first inverter is coupled to an output of the second inverter;

wherein an input of the second inverter is coupled to an output of the first inverter;

wherein the buffer circuit comprises;

a first buffering transistor having a drain coupled to the bit line, a source, and a gate coupled to a SRAM read word line; and

a second buffering transistor having a drain coupled to the source of the first buffering transistor, a source coupled to ground, and a gate coupled to the output of the first inverter; and

wherein the first gate comprises;

a PMOS gate selectively directly electrically coupling the SRAM memory cell to the bit line based upon a complement of the word level word line signal; and

a NMOS gate selectively directly electrically coupling the SRAM memory cell to the bit line based upon the word level word line signal.

9. The NVSRAM of claim 8, further comprising control logic configured to generate the word level word line signal and the complement of the word level word line signal as a function of a word line signal for the SRAM memory cell and a set signal.

10. The NVSRAM of claim 8, wherein the NVSRAM cell further comprises a control gate latch configured to generate the control gate signal.

11. The NVSRAM of claim 10, wherein the control gate latch is configured to be set when both of an erase signal and a power source signal are at a logic high, and is configured to be reset when a read signal is at a logic high.

12. The NVSRAM of claim 10, wherein the control gate latch is configured to be set when both of a program signal and a complement of a power source signal are at a logic high, and is configured to be reset when a read signal is at a logic high.

13. A method of operating a non-volatile static random access memory (NVSRAM), comprising a plurality of words, each of the plurality of words comprising a plurality of NVSRAM cells, each of the plurality of NVSRAM cells comprising a singular SRAM cell and a singular electronically eraseable programmable read only memory (EEPROM) cell, the method comprising steps of:

prior to reading a given word, powering up the NVSRAM but not powering up or initializing any of the plurality of words;

reading a given word by reading each singular EEPROM cell of each of the plurality of NVSRAM cells of the given word, if a given word has not undergone a volatile write command since powerup; and

reading the given word by reading each singular SRAM cell of each of the plurality of NVSRAM cells of the given word, if the given word has undergone a volatile write command since powerup;

wherein reading each singular EEPROM cell comprises, for that singular EEPROM cell, coupling the singular EEPROM cell to a bit line through a dedicated EEPROM sense amplifier for that singular EEPROM cell.

14. The method of claim 13, further comprising:

writing data to the singular SRAM cells of the plurality of NVSRAM cells of the given word through a SRAM write interface;

reloading the singular SRAM cells of the plurality of NVSRAM cells of the given word, in response to selection of that given word; and

wherein the reloading is performed by powering the given word and coupling the singular EEPROM cells of the plurality of NVSRAM cells of the given word to respective singular SRAM cells of the plurality of NVSRAM cells of the given word through the SRAM write interface.