Read window budget based dynamic program step characteristic adjustment

• US 10,706,935 B2
• Filed: 12/10/2018
• Issued: 07/07/2020
• Est. Priority Date: 12/10/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liikanen, Bruce A.
• Primary Examiner(s): Oberly, Eric T
• Application Number:
  US16/214,326
• Publication Number:
  US 20200185034A1
• Time in Patent Office: 575 Days
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A read window budget (RWB) corresponding a group of memory cells is determined. The determined RWB and a target RWB is compared. In response to the determined RWB being different than the target RWB, one or more program step characteristics are adjusted to adjust the determined RWB toward the target RWB.

Claims

1. A system, comprising:

a memory component including a group of memory cells; and

a processing device coupled to the memory component and configured to;

determine a read window budget (RWB) corresponding to the group of memory cells, wherein the RWB is a cumulative value of a number of distances between adjacent threshold voltage distributions associated with the group of memory cells at a particular bit error rate (BER);

compare the determined RWB to a target RWB; and

in response to the determined RWB being different than the target RWB, adjust one or more program step characteristic to adjust the determined RWB toward the target RWB wherein the one or more program step characteristics comprises a step size that corresponds to a voltage difference between consecutive programming signals of a series of programming signals applied to the group of memory cells to program the group of memory cells to a particular data state.

2. The system of claim 1, wherein the one or more program step characteristics further comprises a step duration of at least one of the series of programming signals applied to the group of memory cells.

3. The system of claim 2, wherein the processing device is further configured to adjust the step size without adjusting the step duration of the programming signal to adjust the determined RWB to the target RWB.

4. The system of claim 2, wherein the processing device is further configured to adjust the step duration without adjusting the step size of the programming signal to adjust the determined RWB to the target RWB.

5. The system of claim 1, wherein the memory component comprises a plurality of pages and the group of memory cells corresponds to more than one of the plurality of pages.

6. The system of claim 1, wherein the memory component comprises a plurality of pages and the group of memory cells corresponds to a particular page of the plurality of pages.

7. The system of claim 6, wherein the particular page is randomly selected from among the plurality of pages.

8. A method, comprising:

determining a read window budget (RWB) corresponding to a group of memory cells programmed to a particular data state via a programming signal having one or more program step characteristics, wherein;

an RWB is a cumulative value of a number of distances between adjacent threshold voltage distributions associated with the group of memory cells at a particular bit error rate (BER); and

the one or more programming characteristics comprises a program step duration corresponding to a duration for which the programming signal is applied;

comparing the determined RWB to a target RWB;

in response to the determined RWB being different than the target RWB, adjusting the one or more program step characteristics to adjust the determined RWB to an adjusted RWB;

comparing the adjusted RWB to the target RWB; and

in response to the adjusted RWB being different than the target RWB, further adjusting the one or more program step characteristics to adjust the adjusted RWB toward the target RWB.

9. The method of claim 8, wherein:

the one or more program step characteristics further comprises a program step size; and

the method further comprises decreasing the program step size and the program step duration each by a respective particular amount in response to determining that the determined RWB is less than the target RWB.

10. The method of claim 8, wherein:

the one or more program step characteristics further comprises a program step size; and

the method further comprises increasing the program step size and the program step duration each by a respective particular amount in response to determining that the determined RWB satisfies a threshold associated with the target RWB.

11. The method of claim 8, further comprising repeating a comparison of a previously adjusted RWB to the target RWB.

12. The method of claim 11, wherein the method further comprises, in response to the previously adjusted RWB being different than the target RWB, adjusting the one or more program step characteristics until the previously adjusted RWB is the target RWB.

13. A system, comprising:

a memory component including a group of memory cells; and

a processing device coupled to the memory component and configured to;

determine a read window budget (RWB) corresponding to the group of memory cells, wherein the RWB is determined based on respective read windows between a plurality of threshold voltage distributions corresponding to respective data states to which the group of memory cells are programmed;

compare the determined RWB to a target RWB; and

in response to the determined RWB being different than the target RWB, adjust one or more program step characteristics by a respective determined amount to adjust the RWB toward the target RWB; and

wherein the processing device is further configured to;

determine, using an interpolation, voltages corresponding to two adjacent edges of respective threshold voltage distributions of the plurality of threshold voltage distributions at a particular bit error rate (BER), wherein the interpolation is based on a first read level voltage whose corresponding BER is lower than the particular BER and a second read level voltage whose corresponding BER is greater than the particular BER;

use the determined voltages corresponding to the two adjacent edges to determine a respective one of the read windows; and

determine the RWB by a summation of the determined read windows.

14. The system of claim 13, wherein the one or more programs step characteristics comprises a program step size and a program step duration, and the respective determined amount is based on a determined relationship between the program step size and the program step duration.

15. The system of claim 13, wherein the processing device is further configured to repeatedly adjust the one or more program step characteristics to maintain a constant RWB at the target RWB.

16. The system of claim 13, wherein the processing device is further configured to determine the RWB at periodic intervals.

17. The system of claim 13, wherein the processing device is further configured to determine the RWB responsive to a determination that the group of memory cells has experienced a threshold level of wear cycling.

18. The system of claim 13, wherein the processing device is further configured to determine the RWB responsive to a determination that a temperature change of the memory component has reached a threshold level.

19. The system of claim 13, wherein the processing device is further configured to determine the RWB based on an input/output workload corresponding to the memory component.