Double-biased three-dimensional one-time-programmable memory

• US 10,706,945 B2
• Filed: 09/09/2018
• Issued: 07/07/2020
• Est. Priority Date: 04/14/2016
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Lozada, Alfredo Bermudez
• Application Number:
  US16/125,714
• Publication Number:
  US 20180366207A1
• Time in Patent Office: 667 Days
• Field of Search: 365 94, 365 96, 365104, 365129
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2216/12 Reading and writing aspects of erasable programmable read-only memories
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) comprises an OTP array stacked on a semiconductor substrate. The OTP array comprises a dummy word line, a plurality of data word lines and data bit lines. The dummy OTP cells at the intersections of the dummy word line and all data bit lines are unprogrammed. During read, both voltages on the dummy word line and a selected data word line are raised.

Claims

1. A three-dimensional one-time-programmable read-only memory (3D-OTP) including a semiconductor substrate and an OTP array stacked thereon, said OTP array comprising:

a plurality of data word lines including and a plurality of data bit lines,

a dummy word line in parallel with said data word lines, wherein all dummy OTP cells at the intersections of said dummy word line and said data bit lines are in an unprogrammed state during read;

a first dummy bit line in parallel with said data bit lines, wherein all dummy OTP cells at the intersection of said data word lines and said first dummy bit line are in said unprogrammed state during read;

a first dummy OTP cell at the intersection of said dummy word line and said first dummy bit line is in a first programmed state during read;

a second dummy bit line in parallel with said data bit lines, wherein all dummy OTP cells at the intersection of said data word lines and said second dummy bit line are in said unprogrammed state during read;

a second dummy OTP cell at the intersection of said dummy word line and said second dummy bit line is in a second programmed state during read;

wherein both voltages on said dummy word line and selected one of said data word lines are raised during read;

wherein said first dummy OTP cell in said first programmed state and said second dummy OTP cell in said second programmed state have different resistances.

2. The 3D-OTP according to claim 1, further comprising a differential amplifier whose input is coupled with said first and second dummy bit lines.

3. A semiconductor memory array, comprising:

a plurality of data word lines and a plurality of data bit lines;

a dummy word line in parallel with said data word lines, wherein all dummy cells at the intersections of said dummy word line and said data bit lines are in an unprogrammed state during read;

a first dummy bit line in parallel with said data bit lines, wherein all dummy cells at the intersection of said data word lines and said first dummy bit line are in said unprogrammed state during read;

a first dummy cell at the intersection of said dummy word line and said first dummy bit line is in a first programmed state during read;

a second dummy bit line in parallel with said data bit lines, wherein all dummy cells at the intersection of said data word lines and said second dummy bit line are in said unprogrammed state during read;

a second dummy cell at the intersection of said dummy word line and said second dummy bit line is in a second programmed state during read;

wherein both voltages on said dummy word line and selected one of said data word lines are raised during read;

wherein said first dummy cell in said first programmed state and said second dummy cell in said second programmed state have different resistances.

4. The memory array according to claim 3, further comprising a differential amplifier whose input is coupled with said first and second dummy bit lines.