Fin field-effect transistor and fabrication method thereof

• US 10,707,134 B2
• Filed: 11/13/2017
• Issued: 07/07/2020
• Est. Priority Date: 11/14/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Liu, Ji Quan
• Primary Examiner(s): Vu, David
• Application Number:
  US15/810,398
• Publication Number:
  US 20180144987A1
• Time in Patent Office: 967 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.

Claims

1. A method for fabricating a fin field-effect transistor (FinFET) structure, comprising:

forming a semiconductor substrate and a plurality of fins by etching a base substrate, wherein first trenches and second trenches are formed between adjacent fins, and a width of the first trenches is greater than a width of the second trenches;

forming a first isolation layer on a surface of the semiconductor substrate exposed by the fins and on side surfaces of the fins, wherein the first isolation layer in the first trench contains an opening and has a thickness of the first isolation layer on the surface of the semiconductor substrate and on the side surfaces of the fins in the first trench substantially equals a thickness of the first isolation layer in the second trenches, a volume of the first isolation layer in the first trench equals a volume of the first isolation layer in each of the second trenches, and the first isolation layer in the first trench completely covers the surface of the semiconductor substrate exposed by the fins and the side surfaces of the fins;

performing a first thermal annealing process on the first isolation layer;

forming a second isolation layer to fill the opening and cover the first isolation layer, wherein the second isolation layer has a concave-shaped top surface in the opening;

performing a second thermal annealing process on the second isolation layer;

after performing the second thermal annealing process, removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure;

forming a gate structure across the plurality of fins by covering side and top surfaces of the plurality of fins; and

forming doped source/drain regions in the fins at two sides of the gate structure.

2. The method according to claim 1, wherein:

the first thermal annealing process is one of a furnace thermal annealing process, a rapid thermal annealing process, a heat thermal annealing process, a spike thermal annealing process and a laser thermal annealing process.

3. The method according to claim 1, wherein:

a gas environment of the first thermal annealing process includes one of Ar, N₂ and He;

a temperature of the first thermal annealing process is in a range of approximately 500°

C.-800°

C.; and

a time of the first thermal annealing process is in a range approximately 5 mins-60 mins.

4. The method according to claim 1, wherein forming the first isolation layer comprises:

forming at least one first isolation film on the surface of the semiconductor substrate exposed by the plurality of fins and the side surfaces of the fins;

performing a hardening thermal annealing process to the at least one first isolation film; and

patterning the at least one first isolation film to form the first isolation layer.

5. The method according to claim 4, further comprising:

forming a first isolation material film used to form the first isolation film on the semiconductor substrate exposed by the plurality of fins and the side surfaces of the fins.

6. The method according to claim 1, wherein:

the first isolation layer fills the second trenches.

7. The method according to claim 1, wherein:

the second thermal annealing process is one of a furnace thermal annealing process, a rapid thermal annealing process, a heat thermal annealing process, a spike thermal annealing process and a laser thermal annealing process.

8. The method according to claim 1, wherein:

a gas environment of the second thermal annealing process includes one of Ar, N₂ and He;

a temperature of the second thermal annealing process is in a range of approximately 500°

C.-800°

C.; and

a time of the second thermal annealing process is in a range approximately 5 mins-60 mins.

9. The method according to claim 1, wherein:

each of the first isolation layer and the second isolation layer is formed by one of a flowable chemical vapor deposition process and an atomic layer deposition process.

10. The method according to claim 9, wherein forming the first isolation layer and the second isolation layer comprises:

forming an oxide containing nitrogen bonds and hydrogen bond using trisilyamine (TSA) and NH₃ as precursors; and

processing the oxide containing nitrogen bonds and hydrogen bonds using O₃.

11. The method according to claim 10, wherein:

the oxide containing nitrogen bonds and hydrogen bonds is silicon dioxide.

12. The method according to claim 1, wherein:

a width the first trench is in a range of approximately 80 nm-200 nm; and

a width of the second trench is in a range of approximately 20 nm-80 nm.

13. The method according to claim 1, wherein:

the base substrate includes a first region and a second region, used for forming different transistors;

the first trenches are between adjacent fins at a boundary region between the first region and the second region; and

the second trenches are between adjacent fins in the first region or adjacent fins in the second region.

14. The method according to claim 1, wherein forming the semiconductor substrate and the plurality of fins by etching the base substrate comprises:

providing the base substrate;

forming a hard mask layer on the base substrate; and

etching the base substrate using the hard mask layer as a mask.

15. The method according to claim 14, before removing the partial thickness of the first isolation layer and the partial thickness of the second isolation layer and after forming the second isolation layer, further comprising:

performing a planarization process on the first isolation layer and the second isolation layer using the hard mask layer as a stop layer.

16. The method according to claim 1, wherein:

a thickness of the first isolation layer in the first trench equals a thickness of the first isolation layer in the second trenches.