Cascode semiconductor device structure and method therefor

• US 10,707,203 B2
• Filed: 12/19/2018
• Issued: 07/07/2020
• Est. Priority Date: 10/28/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Padmanabhan, Balaji, Venkatraman, Prasad, Hossain, Zia, Liu, Chun-Li, Jeon, Woochul, McDonald, Jason
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US16/225,930
• Publication Number:
  US 20190123043A1
• Time in Patent Office: 566 Days
• Field of Search: 257192
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming a cascode rectifier structure includes providing a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are provided adjacent a major surface of the heterostructure and a control electrode is provided between the first and second current carrying electrode. A rectifier device is provided integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is provided further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is provided as a two terminal device.

Claims

1. A method of forming a semiconductor device structure, comprising:

providing a substrate structure comprising;

a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises a first doped region having a first conductivity type adjacent the second major surface; and

a heterostructure adjacent to the first major surface, wherein the heterostructure comprises;

a channel layer comprising a group III-V material; and

a barrier layer disposed over the channel layer and comprising a group III-V material;

providing a first electrode disposed proximate to a first portion of the channel layer;

providing a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;

providing a control electrode, wherein the control electrode is proximate to the channel layer and disposed between the first electrode and the second electrode and is configured to control a first current path in the channel layer between the first electrode and the second electrode;

providing a second doped region of a second conductivity type opposite to the first conductivity type disposed in the semiconductor region such that the first doped region and the second doped region provide a rectifier device;

providing a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically coupled to the first electrode and electrically coupled to the second doped region;

providing a second trench electrode extending through the heterostructure and into the semiconductor substrate to at least the first doped region; and

providing a third electrode disposed adjacent to the second major surface, wherein;

the second trench electrode electrically connects the control electrode to the third electrode through the semiconductor substrate;

the rectifier device is electrically coupled to the first trench electrode and electrically coupled to the third electrode, but is electrically decoupled from the second electrode; and

the semiconductor device is configured as a two terminal device.

2. The method of claim 1, wherein:

providing the first electrode comprises providing a source electrode that overlaps the first trench electrode; and

the second electrode comprises a drain electrode.

3. The method of claim 2, wherein:

providing the first trench electrode comprises providing the first trench electrode inset from at least one side surface of the first electrode.

4. The method of claim 1, wherein:

providing the second doped region comprises providing the second doped region such that the second doped region and the second electrode overlap.

5. The method of claim 1, further comprising:

providing a third doped region of the first conductivity type disposed between the semiconductor substrate and the heterostructure.

6. A method of forming a semiconductor device comprising:

providing a substrate structure comprising;

a semiconductor substrate having a first major surface and an opposing second major surface;

a heterostructure disposed over the first major surface, the heterostructure comprising;

a group III-V channel layer; and

a group III-V barrier layer over the group III-V channel layer;

providing a first electrode disposed proximate to a first portion of the group III-V channel layer;

providing a second electrode disposed proximate to a second portion of the group III-V channel layer and spaced apart from the first electrode;

providing a control electrode disposed between the first electrode and the second electrode;

providing a third electrode disposed adjacent to the second major surface of the semiconductor substrate;

providing a rectifier device as part of the semiconductor substrate; and

providing a fourth electrode electrically coupled to the first electrode and the rectifier device, wherein;

the rectifier device is electrically decoupled from the second electrode; and

the control electrode is electrically connected to the third electrode through the semiconductor substrate to provide the semiconductor device as a two terminal device.

7. The method of claim 6, wherein:

providing the rectifier device comprises providing a first doped region having a first conductivity type such that a lower surface of the fourth electrode adjoins the first doped region; and

providing the semiconductor substrate comprises;

providing a semiconductor region adjacent the first doped region and comprising a second conductivity type opposite to the first conductivity type; and

providing a second doped region having the second conductivity type and adjoining the second major surface, wherein the second doped region has a higher dopant concentration than the semiconductor region.

8. The semiconductor device of claim 7, wherein:

providing the fourth electrode comprises providing a first trench electrode extending through the hetero structure; and

providing the control electrode comprises electrically connecting the control electrode to the second doped region with a second trench electrode extending through the heterostructure into the semiconductor substrate.

9. The method of claim 8 further comprising:

providing a third doped region of the second conductivity type disposed adjoining an interface between the heterostructure and the semiconductor substrate.

10. The method of claim 8, wherein:

providing the heterostructure comprises providing a portion of the heterostructure proximate to the first trench electrode devoid of the channel region.

11. The method of claim 10, wherein:

providing the second trench electrode comprises;

providing a trench extending through the heterostructure into the semiconductor substrate;

providing a dielectric material along sidewall surfaces of the trench; and

providing a conductive electrode within the trench so that the dielectric material is disposed between the sidewall surfaces of the trench and the conductive electrode.

12. The method of claim 6, wherein:

providing the rectifier device comprises providing a Schottky rectifier device.

13. A method of forming a semiconductor device comprising:

providing a semiconductor substrate having a first major surface and an opposing second major surface;

providing a rectifier device disposed in the semiconductor substrate;

providing a heterostructure adjacent the first major surface, the heterostructure comprising;

a channel layer; and

a barrier layer over the channel layer;

providing a first electrode disposed proximate to a first portion of the channel layer;

providing a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;

providing a control electrode disposed proximate to the channel layer and between the first electrode and the second electrode and configured to control a first current path between the first electrode and the second electrode;

providing a first trench electrode extending through the heterostructure into the semiconductor substrate and electrically connected to the first electrode; and

providing a third electrode disposed on the second major surface of the semiconductor substrate, wherein;

the rectifier device is electrically connected to the first trench electrode and electrically connected to the third electrode, but not electrically connected to the second electrode,

the rectifier device is configured to provide a second current path generally perpendicular to the first current path, and

the control electrode is electrically coupled to the third electrode through the semiconductor substrate to provide the semiconductor device as a two-terminal device.

14. The method of claim 13, further comprising:

providing a second trench electrode electrically connecting the control electrode to the third electrode through the semiconductor substrate.

15. The method of claim 14, wherein providing the second trench electrode comprises:

providing a trench extending from the first major surface at least to the semiconductor substrate;

providing a dielectric material along sidewall surfaces of the trench; and

providing a conductive material adjacent to the dielectric material.

16. The method of claim 13, wherein:

providing the rectifier device comprises providing a first doped region such that the first doped region adjoins a lower surface of the first trench electrode, the first doped region having a first conductivity type; and

providing the semiconductor substrate comprises;

providing a semiconductor region adjacent the first doped region and comprising a second conductivity type opposite to the first conductivity type; and

providing a second doped region having the second conductivity type and adjoining the second major surface, wherein the second doped region has a higher dopant concentration than the semiconductor region, and wherein the first doped region is interposed between at least a portion of the semiconductor region and the second doped region such that the semiconductor region separates the first doped region from the heterostructure.

17. The method of claim 16, further comprising:

providing a third doped region of the second conductivity type disposed between the semiconductor region and the hetero structure.

18. The method of claim 16, wherein:

providing the first doped region comprises laterally extending the first doped region so that the first control electrode laterally overlaps the first doped region.

19. The method of claim 13, wherein:

providing the heterostructure comprises;

providing the channel layer comprising a group III-V material; and

providing the barrier layer comprising a group III-V material; and

providing the first electrode comprises providing the first electrode laterally overlapping the first trench electrode.

20. The method of claim 13, wherein providing the first trench electrode comprises:

providing a trench extending through the heterostructure into the semiconductor substrate;

providing a dielectric material along sidewall surfaces of the trench; and

providing a conductive material adjacent the dielectric material.