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Asymmetric semiconductor memory device having electrically floating body transistor

  • US 10,707,209 B2
  • Filed: 08/14/2018
  • Issued: 07/07/2020
  • Est. Priority Date: 03/24/2011
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a semiconductor memory array comprising a plurality of asymmetric bi-stable semiconductor memory cells arranged in a matrix of rows and columns, wherein each said asymmetric bi-stable semiconductor memory cell includes;

    a first bipolar device having a first floating base region, a first emitter, and a first collector; and

    a second bipolar device having a second floating base region, a second emitter, and a second collector,wherein said first floating base region and said second floating base region comprise a common floating base region and wherein said common floating base region comprises means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;

    wherein said first collector is common to said second collector;

    wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, andwherein performance characteristics of said first bipolar device are different from performance characteristics of said second bipolar device;

    wherein one of said first emitter or second emitter comprises an electrode electrically connected to said first floating base region and second floating base region, wherein said electrode forms a Schottky contact with said first floating base region and second floating base region; and

    a control circuit configured to perform a holding operation on said array.

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