Asymmetric semiconductor memory device having electrically floating body transistor

• US 10,707,209 B2
• Filed: 08/14/2018
• Issued: 07/07/2020
• Est. Priority Date: 03/24/2011
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Duy T
• Application Number:
  US16/102,896
• Publication Number:
  US 20180374854A1
• Time in Patent Office: 693 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7308 Schottky transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Claims

1. An integrated circuit comprising:

a semiconductor memory array comprising a plurality of asymmetric bi-stable semiconductor memory cells arranged in a matrix of rows and columns, wherein each said asymmetric bi-stable semiconductor memory cell includes;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector,

wherein said first floating base region and said second floating base region comprise a common floating base region and wherein said common floating base region comprises means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, and

wherein performance characteristics of said first bipolar device are different from performance characteristics of said second bipolar device;

wherein one of said first emitter or second emitter comprises an electrode electrically connected to said first floating base region and second floating base region, wherein said electrode forms a Schottky contact with said first floating base region and second floating base region; and

a control circuit configured to perform a holding operation on said array.

2. The integrated circuit of claim 1, wherein said asymmetric bi-stable semiconductor memory cell further comprises a gate positioned above said common floating base region.

3. The integrated circuit of claim 2, wherein said asymmetric bi-stable semiconductor memory cell further comprises:

a substrate; and

a buried layer;

wherein said buried layer comprises said first and second collectors; and

wherein said substrate is separated from said common floating base region by said buried layer.

4. The integrated circuit of claim 2, wherein said asymmetric bi-stable semiconductor memory cell further comprises a gap region on a surface of said common floating base region, said gap region located between one of said first bipolar device or second bipolar device and said gate.

5. The integrated circuit of claim 3, further comprising:

a word line terminal electrically connected to said gate;

a bit line terminal electrically connected to said first emitter;

a source line terminal electrically connected to said second emitter;

a buried well terminal electrically connected to said buried layer; and

a substrate terminal electrically connected to said substrate.

6. The integrated circuit of claim 2, wherein said asymmetric bi-stable semiconductor memory cell further comprises an insulating layer insulating said gate from said common floating base region.

7. The integrated circuit of claim 1, wherein:

said common floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first collector and said second collector have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, said second conductivity type being different from said first conductivity type; and

a second region having said second conductivity type, said second region being separated from at least one of said first and second collectors by said common floating base region.

8. The integrated circuit of claim 1, wherein said asymmetric bi-stable semiconductor memory cell has a fin structure.

9. The integrated circuit of claim 1, wherein said control circuit provides electrical signals to at least two of said memory cells to maintain the states of said at least two memory cells.

10. The integrated circuit of claim 9, wherein said electrical signals are constant voltage biases.

11. The integrated circuit of claim 9, wherein said electrical signals are periodic pulses of voltage.

12. The integrated circuit of claim 9, wherein said electrical signals result in at least two stable states.

13. The integrated circuit of claim 1, wherein said control circuit comprises a voltage generator circuit.

14. The integrated circuit of claim 13, further comprising a multiplexer electrically connected between said voltage generator circuit and said first and second collectors.

15. The integrated circuit of claim 1, further comprising a semiconductor memory cell connected to at least one of said asymmetric bi-stable semiconductor memory cells, said semiconductor memory cell comprising:

a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;

said floating body region comprising means for storing a charge or lack of charge indicative of a state of the semiconductor memory cell;

a first region having said first conductivity type and being in direct contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having a second conductivity type selected from said n-type and said p-type conductivity type, said second conductivity type being different from said first conductivity type.

16. The integrated circuit of claim 15, wherein said semiconductor memory cell is useable as a reference cell by applying an intermediate potential between a first potential indicative of a logic-0 state and second potential indicative of a logic-1 state to said floating body region through said first region.

17. The integrated circuit of claim 15, wherein said semiconductor memory cell is configured for use as a reference cell, further comprising a third region in electrical contact with said floating body region, said third region having said second conductivity type.