Asymmetric semiconductor memory device having electrically floating body transistor
First Claim
1. An integrated circuit comprising:
- a semiconductor memory array comprising a plurality of asymmetric bi-stable semiconductor memory cells arranged in a matrix of rows and columns, wherein each said asymmetric bi-stable semiconductor memory cell includes;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector,wherein said first floating base region and said second floating base region comprise a common floating base region and wherein said common floating base region comprises means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell;
wherein said first collector is common to said second collector;
wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, andwherein performance characteristics of said first bipolar device are different from performance characteristics of said second bipolar device;
wherein one of said first emitter or second emitter comprises an electrode electrically connected to said first floating base region and second floating base region, wherein said electrode forms a Schottky contact with said first floating base region and second floating base region; and
a control circuit configured to perform a holding operation on said array.
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Abstract
Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.
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Citations
17 Claims
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1. An integrated circuit comprising:
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a semiconductor memory array comprising a plurality of asymmetric bi-stable semiconductor memory cells arranged in a matrix of rows and columns, wherein each said asymmetric bi-stable semiconductor memory cell includes; a first bipolar device having a first floating base region, a first emitter, and a first collector; and a second bipolar device having a second floating base region, a second emitter, and a second collector, wherein said first floating base region and said second floating base region comprise a common floating base region and wherein said common floating base region comprises means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell; wherein said first collector is common to said second collector; wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, and wherein performance characteristics of said first bipolar device are different from performance characteristics of said second bipolar device; wherein one of said first emitter or second emitter comprises an electrode electrically connected to said first floating base region and second floating base region, wherein said electrode forms a Schottky contact with said first floating base region and second floating base region; and a control circuit configured to perform a holding operation on said array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification