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Resistive memory cell having a compact structure

  • US 10,707,270 B2
  • Filed: 03/18/2019
  • Issued: 07/07/2020
  • Est. Priority Date: 06/23/2015
  • Status: Active Grant
First Claim
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1. A process for fabricating an integrated circuit having a first memory cell, the process comprising:

  • forming a selection transistor of the first memory cell on a semiconductor substrate covered with a first insulating layer, the first insulating layer being covered with a semiconductive active layer, the selection transistor including a control gate and first and second conduction terminals;

    covering with a second insulating layer a lateral flank of the control gate on a same side as the first conduction terminal;

    producing a first trench through the active layer in the first conduction terminal, reaching the first insulating layer;

    depositing a layer of a variable-resistance material in the first trench, covering a lateral flank of the active layer in the first trench; and

    forming, in the layer of variable-resistance material, a trench conductor reaching the first insulating layer.

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