Silicon carbide semiconductor device, and method for manufacturing same

• US 10,707,299 B2
• Filed: 05/14/2015
• Issued: 07/07/2020
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Shiomi, Hiromu
• Primary Examiner(s): Kim, Jay C
• Application Number:
  US15/129,542
• Publication Number:
  US 20170110534A1
• Time in Patent Office: 1,881 Days
• Field of Search: 257 77
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region. The gate insulating film is in contact with the first region, the second impurity region, and the third impurity region at a side portion of a trench.

Claims

1. A silicon carbide semiconductor device comprising:

a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including a first impurity region, a second impurity region, and a third impurity region, the first impurity region having a first conductivity type, the second impurity region being in contact with the first impurity region and having a second conductivity type different from the first conductivity type, the third impurity region having the first conductivity type and being separated from the first impurity region by the second impurity region, the first impurity region including a first region, a second region, and a third region, the first region being in contact with the second impurity region, the second region being in contact with the first region, the second region being located opposite to the second impurity region when viewed from the first region, the second region having an impurity concentration higher than an impurity concentration of the first region, the third region being in contact with the second region, the third region being located opposite to the first region when viewed from the second region, the third region having an impurity concentration lower than the impurity concentration of the second region, a trench being formed in the first main surface of the silicon carbide substrate to have a side portion and a bottom surface, the side portion being continuous to the first main surface, the bottom surface being continuous to the side portion, the silicon carbide substrate further including;

an embedded region that has the second conductivity type, that has an impurity concentration higher than the impurity concentration of the second impurity region, and that extends from a portion of an end portion of the second impurity region at the second main surface side toward the second main surface; and

a contact region that has the second conductivity type, that has an impurity concentration higher than the impurity concentration of the second impurity region, and that connects the first main surface to the embedded region; and

a gate insulating film in contact with the first region, the second impurity region, and the third impurity region at the side portion of the trench, the gate insulating film is in contact with the first region at the bottom surface of the trench;

wherein

the silicon carbide semiconductor device is a metal oxide semiconductor field-effect transistor (MOSFET) device with a drain electrode at a bottom surface of the silicon carbide substrate,

the embedded region is in contact with each of the first region and the second region, and

the embedded region is separated from the third region.

2. The silicon carbide semiconductor device according to claim 1, wherein the impurity concentration of the first region is not more than 1.5×

10¹⁶ cm<sup>−

3</sup>.

3. The silicon carbide semiconductor device according to claim 1, wherein the impurity concentration of the second region is not less than 2×

10¹⁶ cm<sup>−

3</sup>.

4. The silicon carbide semiconductor device according to claim 1, wherein the first region has a thickness of not less than 0.1 μ

m and not more than 0.5 μ

m in a normal direction of the first main surface.

5. The silicon carbide semiconductor device according to claim 1, wherein the second region has a thickness of not less than 0.3 μ

m and not more than 2 μ

m in a normal direction of the first main surface.

6. The silicon carbide semiconductor device according to claim 1, wherein an end portion of the embedded region at the second main surface side is in contact with the second region.

7. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide substrate further includes a buffer layer that has the first conductivity type, that has an impurity concentration higher than the impurity concentration of the third region, and that is in contact with the third region at the second main surface side.