Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts

• US 10,707,303 B1
• Filed: 01/31/2019
• Issued: 07/07/2020
• Est. Priority Date: 01/31/2019
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wang, Haiting, Zang, Hui, Hu, Zhenyu Owen
• Primary Examiner(s): Vu, Vu A
• Application Number:
  US16/264,273
• Time in Patent Office: 523 Days
• Field of Search: 257330
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A semiconductor device, comprising a semiconductor substrate; an isolation layer disposed on the semiconductor substrate; a first active region and a second active region disposed at least partially above the isolation layer; a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region; and an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

an isolation layer disposed on the semiconductor substrate;

a first active region and a second active region disposed at least partially above the isolation layer, wherein the first active region and the second active region each comprise a long axis and a short axis, wherein the long axes of the first and second active regions are substantially parallel and extend in a first direction;

a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region, wherein the first gate structure and the second gate structure each comprise a long axis and a short axis, wherein the long axes of the first and second gate structures are substantially parallel and extend in a second direction, wherein the second direction is substantially perpendicular to the first direction; and

an isolation structure disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation structure has an inverted-T shape in a sectional view taken across the first direction.

2. The semiconductor device of claim 1, wherein the isolation structure comprises silicon nitride.

3. The semiconductor device of claim 1, wherein the semiconductor substrate comprises silicon.

4. The semiconductor device of claim 1, wherein the isolation layer comprises silicon oxide.

5. The semiconductor device of claim 1, wherein the first active region and the second active region are each a nanosheet structure.

6. The semiconductor device of claim 1, wherein the first active region and the second active region are each a component of a fin structure.

7. A method, comprising:

providing a semiconductor substrate;

providing an isolation layer disposed on the semiconductor substrate;

forming a first active region and a second active region disposed at least partially above the isolation layer, wherein the first active region and the second active region each comprise a long axis and a short axis, wherein the long axes of the first and second active regions are substantially parallel and extend in a first direction;

forming a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region, wherein the first gate structure and the second gate structure each comprise a long axis and a short axis, wherein the long axes of the first and second gate structures are substantially parallel and extend in a second direction, wherein the second direction is substantially perpendicular to the first direction;

forming a high-κ

material on the isolation layer, the first active region, the second active region, the first gate structure, and the second gate structure, such that a rectangular portion of the isolation layer between the first active region and the second active region, and between and in contact with the first gate structure and the second gate structure, remains exposed;

forming an isolation pillar material on the rectangular portion of the isolation layer, wherein the isolation pillar material has a rectangular shape in a sectional view taken across the first direction and lower portions of two opposed sides of the isolation pillar material are in contact with the high-κ

material; and

trimming upper portions of the two opposed sides of the isolation pillar material, wherein the upper portions are above the lower portions, to yield an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape in a sectional view taken across the first direction.

8. The method of claim 7, further comprising:

removing the high-κ

material from the isolation layer, the first active region, the second active region, the first gate structure, and the second gate structure.

9. The method of claim 7, further comprising:

performing a replacement metal gate (RMG) process on the first gate structure and the second gate structure.

10. The method of claim 7, wherein forming the isolation pillar material comprises depositing silicon nitride.

11. The method of claim 7, wherein providing the semiconductor substrate comprises structuring a silicon material.

12. The method of claim 7, wherein providing the isolation layer comprises positioning silicon oxide.

13. The method of claim 7, wherein forming the first active region and the second active region comprises forming nanosheet structures.

14. The method of claim 7, wherein forming the first active region and the second active region comprises forming a fin structure.

15. The method of claim 7, wherein forming the first gate structure and the second gate structure each comprise forming a gate poly layer;

a capping layer disposed on the gate poly layer; and

a spacer disposed on sides of the gate poly layer and sides of the capping layer.

16. The method of claim 7, wherein the high-κ

material is selected from the group consisting of hafnium oxide and aluminum oxide.

17. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device; and

a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to;

provide a semiconductor substrate;

provide an isolation layer disposed on the semiconductor substrate;

form a first active region and a second active region disposed at least partially above the isolation layer, wherein the first active region and the second active region each comprise a long axis and a short axis, wherein the long axes of the first and second active regions are substantially parallel and extend in a first direction;

form a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region, wherein the first gate structure and the second gate structure each comprise a long axis and a short axis, wherein the long axes of the first and second gate structures are substantially parallel and extend in a second direction, wherein the second direction is substantially perpendicular to the first direction; and

form an isolation structure disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation structure has an inverted-T shape in a sectional view taken across the first direction.

18. The system of claim 17, wherein the semiconductor device processing system is further adapted to:

perform a replacement metal gate (RMG) process on the first gate structure and the second gate structure.