Semiconductor device

• US 10,707,312 B2
• Filed: 08/31/2018
• Issued: 07/07/2020
• Est. Priority Date: 03/20/2018
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Electronic Devices & Storage Corporation (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuba, Hiroshi, Hung, Hung, Nishiwaki, Tatsuya, Aida, Kikuo, Oasa, Kohei
• Primary Examiner(s): Ward, Eric A.
• Application Number:
  US16/119,983
• Publication Number:
  US 20190296116A1
• Time in Patent Office: 676 Days
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate;

a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies;

a gate layer adjacent to the base layer with a gate insulating film therebetween;

a source layer connected to the base layer;

a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate;

a source wiring layer above the first conductive layer in each of the plurality of first columnar bodies and above at least a part of the second conductive layer, and electrically connected to the first conductive layer in each of the plurality of first columnar bodies and to the second conductive layer in the second columnar body; and

a gate lead-out layer that extends from a first region surrounded by the second columnar body over the second columnar body to a second region outside the first region and is electrically connected to the gate layer, the gate lead-out layer being electrically separated from the first conductive layer in each of the first columnar bodies and the second conductive layer in the second columnar body.

2. The semiconductor device according to claim 1, wherein three adjacent first columnar bodies of the plurality of first columnar bodies are equally spaced from one another.

3. The semiconductor device of claim 1, wherein the source layer is electrically connected to the plurality of first conductive layers.

4. The semiconductor device according to claim 1, further comprising:

a first contact extending between and electrically connecting the source wiring layer and the first conductive layer in each of the plurality of first columnar bodies; and

a second contact connected to the gate lead-out layer.

5. The semiconductor device according to claim 4, wherein the plurality of first columnar bodies are located in a device region of the semiconductor device, and the second contact is located in a terminal region of the semiconductor device.

6. The semiconductor device according to claim 5, wherein the second columnar body is in the terminal region of the semiconductor device.

7. The semiconductor device according to claim 1, wherein the second conductive layer follows the shape of the outer periphery of the plurality of first columnar bodies.

8. The semiconductor device according to claim 1, wherein the gate layer extends as a stripe between two adjacent first columnar bodies among the plurality of the first columnar bodies.

9. The semiconductor device according to claim 1, wherein the gate layer extends as a stripe between a plurality of adjacent first columnar bodies.

10. The semiconductor device according to claim 1, wherein the spacing between the gate layer and an adjacent first columnar body is constant.

11. The semiconductor device according to claim 1, wherein the shape of each of the plurality of the first columnar bodies is the same, and is at least one of a rectangular, a circular, or a regular hexagonal shape.