Power MOSFET with metal filled deep source contact

• US 10,707,344 B2
• Filed: 11/20/2017
• Issued: 07/07/2020
• Est. Priority Date: 01/18/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lin, Furen, Baiocchi, Frank, Liu, Yunlong, Liu, Lark, Lv, Tianping, Lin, Peter, Lin, Ho
• Primary Examiner(s): Stark, Jarrett J
• Application Number:
  US15/817,488
• Publication Number:
  US 20180076320A1
• Time in Patent Office: 960 Days
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Claims

1. A planar gate power metal-oxide-semiconductor field effect transistor die (power MOSFET), comprising:

a substrate having a semiconductor surface layer doped a first conductivity type over a bulk substrate, the semiconductor surface layer having a top side and the bulk substrate having a backside opposite the semiconductor surface layer;

a plurality of transistor cells (cells) including a first cell and at least a second cell formed on the top side of the semiconductor surface layer, the first cell having a first gate stack and the second cell having a second gate stack;

each gate stack including a gate electrode on a gate dielectric over a body region;

a trench having an aspect ratio of at least 3 extending down from the top side of the semiconductor surface layer between the first gate stack and the second gate stack providing a source contact (SCT) from the substrate to a source doped a second conductivity type, and further comprising a substrate contact region at a bottom of the SCT, wherein the substrate contact region is doped the first conductivity type and extends from the semiconductor surface layer into the bulk substrate, the backside of the bulk substrate electrically coupled to the source;

a field plate (FP) over the first and second gate stacks extending to provide a liner for the trench;

the trench having a refractory metal or platinum-group metal (PGM) filler (metal filler) within the trench, and

a drain doped the second conductivity type in the semiconductor surface layer on a side of the first gate stack opposite the trench and on a side of the second gate stack opposite the trench.

2. The power MOSFET of claim 1, wherein the metal filler comprises tungsten (W).

3. The power MOSFET of claim 1, wherein the metal filler comprises Ta, Pt, or Pd, or refractive metal silicides of the Ta, Pt, or Pd.

4. The power MOSFET of claim 1, wherein the gate electrode comprises a metal silicide (WSi₂) on polysilicon.

5. The power MOSFET of claim 1, wherein the FP comprises at least one refractory metal layer.

6. The power MOSFET of claim 1, wherein the bulk substrate comprises a p+ substrate and the semiconductor surface layer comprises a p-epitaxial layer, and wherein the power MOSFET comprises NMOS.

7. The power MOSFET of claim 1, wherein the bulk substrate comprises an n+ substrate and the semiconductor surface layer comprises an n-epitaxial layer, and wherein the power MOSFET comprises PMOS.

8. The power MOSFET of claim 1, wherein the FP comprises at least one refractory metal layer.

9. The device of claim 1, wherein the first gate stack and the second gate stack each include sidewall spacers and the trench is between and self-aligned to the first gate stack and second gate stack.

10. A planar power gate metal-oxide-semiconductor field effect transistor die (power MOSFET), comprising:

a substrate having a semiconductor surface doped a first conductivity type;

a plurality of transistor cells (cells) including a first cell and at least a second cell formed on the semiconductor surface, the first cell having a first gate stack and the second cell having a second gate stack;

each gate stack including a gate electrode on a gate dielectric over a body region, a trench having an aspect ratio of at least 3 extending down from a top side of the semiconductor surface between the first gate stack and the second gate stack providing a source contact (SCT) from the substrate to a source doped a second conductivity type, and a field plate (FP) over the first and second gate stacks extending to provide a liner for the trench;

the trench having a tungsten or tungsten comprising filler within the trench, the filler entirely contained within the trench and having a dielectric layer extending into the trench and covering the filler, the filler contacting the field plate within the trench and the field plate contacting the dielectric above the trench; and

a drain doped the second conductivity type in the semiconductor surface on a side of the first and second gate stacks opposite the trench.

11. The power MOSFET of claim 10, wherein the gate electrode comprises a metal silicide (WSi₂) on polysilicon.

12. The power MOSFET of claim 10, wherein the FP comprises at least one refractory metal layer.

13. The power MOSFET of claim 10, wherein the substrate comprises a p+ substrate and the semiconductor surface comprises a p-epitaxial layer, and wherein the power MOSFET comprises NMOS.

14. The power MOSFET of claim 10, wherein the substrate comprises an n+ substrate and the semiconductor surface comprises an n-epitaxial layer, and wherein the power MOSFET comprises PMOS.

15. The power MOSFET of claim 10, wherein the FP comprises at least one refractory metal layer.

16. The power MOSFET of claim 10, further comprising a substrate contact region at a bottom of the SCT, wherein the substrate contact region is doped the first conductivity type, the substrate comprises a bulk substrate, the semiconductor surface comprises a p-epitaxial layer on the bulk substrate, and the substrate contact region extends below the p-epitaxial layer into the bulk substrate.

20. The device of claim 10, wherein the first gate stack and the second gate stack each include sidewall spacers and the trench is between and self-aligned to the first gate stack and second gate stack.

17. A device including a planar gate power metal-oxide-semiconductor field effect transistor (power MOSFET), comprising:

a substrate having a semiconductor surface doped a first conductivity type;

a first gate stack and a second gate stack, the first and second gate stacks each including sidewall spacers and a gate electrode on a gate dielectric over a body region;

a trench having an aspect ratio of at least 3 extending down from a top side of the semiconductor surface between and self-aligned to the first gate stack and the second gate stack, the trench providing a source contact (SCT) from the substrate to a source doped a second conductivity type;

a field plate (FP) over the first and second gate stacks extending to provide a liner for the trench, wherein the trench has a refractory metal or platinum-group metal (PGM) filler (metal filler) within the trench, the metal filler contained entirely within the trench and the metal filler and the trench covered by a dielectric; and

a drain doped the second conductivity type in the semiconductor surface on a side of the first and second gate stacks opposite the trench.

18. The device of claim 17, wherein the metal filler comprises tungsten (W).

19. The device of claim 17, wherein the metal filler comprises Ta, Pt, or Pd, or refractive metal silicides of Ta, Pt, or Pd.