Fin field effect transistors having liners between device isolation layers and active areas of the device

• US 10,707,348 B2
• Filed: 09/30/2019
• Issued: 07/07/2020
• Est. Priority Date: 09/01/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sung, Sug-Hyun, You, Jung-gun, Park, Gi-gwan, Kim, Ki-il
• Primary Examiner(s): Enad, Christine A
• Application Number:
  US16/587,227
• Publication Number:
  US 20200027986A1
• Time in Patent Office: 281 Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Claims

1. An integrated circuit device comprising:

a first fin-type active area protruding from a first region of a substrate and comprising a first channel region of a first conductivity type;

a plurality of liners covering lower side walls of the first fin-type active area on the first region, wherein the plurality of liners comprise a first insulating liner and a first stress liner including materials different from each other, wherein the first insulating liner contacts the lower side walls of the first fin-type active area and has a first upper surface at a first height from the substrate, wherein the first stress liner is spaced apart from the lower side walls of the first fin-type active area and has a second upper surface at a second height from the substrate, and wherein the first insulating liner is between the first stress liner and the lower side walls of the first fin-type active area, and the second height is higher than the first height;

a first device isolation layer covering the lower side walls of the first fin-type active area, wherein the plurality of liners are between the first device isolation layer and the lower side walls of the first fin-type active area on the first region;

a first gate insulating layer on the first region, the first gate insulating layer extending to cover the first channel region of the first fin-type active area, the plurality of liners, and the first device isolation layer, and comprising first protrusions located on portions of the first gate insulating layer which cover the plurality of liners;

a second fin-type active area protruding from a second region of the substrate and comprising a second channel region of a second conductivity type;

a second device isolation layer covering lower side walls of the second fin-type active area on the second region;

a second insulating liner covering the lower side walls of the second fin-type active area, wherein the second insulating liner is between the second fin-type active area and the second device isolation layer on the second region; and

a second gate insulating layer on the second region, the second gate insulating layer extending to cover the second channel region, the second insulating liner, and the second device isolation layer.

2. The integrated circuit device of claim 1,

wherein the substrate comprises a trench defining the second fin-type active area in the second region,

wherein the second insulating liner comprises a side wall extension between the second fin-type active area and the second device isolation layer in the trench, and a bottom extension connected integrally to the side wall extension and being between a bottom surface of the trench and the second device isolation layer, and

wherein the side wall extension of the second insulating liner has a first thickness and the bottom extension of the second insulating liner has a second thickness, wherein the first thickness is greater than the second thickness.

3. The integrated circuit device of claim 1,

wherein the second insulating liner and the second device isolation layer contact each other.

4. The integrated circuit device of claim 1, further comprising a second stress liner between the second insulating liner and the second device isolation layer on the second region,

wherein the second insulating liner has a third upper surface at a third height from the substrate, the second stress liner has a fourth upper surface at a fourth height from the substrate, wherein the fourth height is higher than the third height, and a height difference between the third upper surface and the fourth upper surface is smaller than a height difference between the first upper surface and the second upper surface.

5. An integrated circuit device comprising:

a fin-type active area protruding from a substrate;

a first liner extending along a first lower side wall of the fin-type active area and spaced apart therefrom;

a first device isolation layer covering the first lower side wall of the fin-type active area,

wherein the first liner is between the first device isolation layer and the first lower side wall of the fin-type active area and an upper end of the first liner protrudes from an upper surface of the first device isolation layer;

a second liner covering a second lower side wall of the fin-type active area,

wherein the second lower side wall is opposite to the first lower side wall;

a second device isolation layer covering the second lower side wall of the fin-type active area, wherein the second liner is between the second device isolation layer and the second lower side wall of the fin-type active area; and

a first gate insulating layer extending to cover the fin-type active area, the first liner, and the first device isolation layer, and comprising a first protrusion which cover the upper end of the first liner,

wherein the first protrusion of the first gate insulating layer contacts an upper surface of the upper end of the first liner and opposite side walls thereof.

6. The integrated circuit device of claim 5,

wherein the fin-type active area has a cross-sectional profile of opposite side walls in a shorter axis direction, wherein the cross-sectional profile has an asymmetric shape.

7. The integrated circuit device of claim 5, further comprising a second gate insulating layer extending to cover the fin-type active area, the second liner, and the second device isolation layer, and connected integrally to the first gate insulating layer.

8. The integrated circuit device of claim 7,

wherein the first gate insulating layer and the second gate insulating layer are asymmetric about the fin-type active area.

9. The integrated circuit device of claim 7,

wherein the second gate insulating layer comprises second protrusions located on portions of the second gate insulating layer which cover the second liner.

10. The integrated circuit device of claim 7,

wherein respective thicknesses of the first gate insulating layer and the second gate insulating layer are different from each other.

11. The integrated circuit device of claim 5,

wherein the substrate comprises a first conductivity type transistor region and a second conductivity type transistor region that are adjacent to each other, and

wherein the fin-type active area extends along a boundary between the first conductivity type transistor region and the second conductivity type transistor region.

12. An integrated circuit device comprising:

a fin-type active area disposed on a substrate;

a liner covering at least a portion of side walls of the fin-type active area;

a device isolation layer disposed on the liner;

a gate insulating layer disposed on the liner and on the device isolation layer, the gate insulating layer including protrusions covering the liner; and

a gate line covering the gate insulating layer and a channel region of the fin-type active area,

wherein the gate line comprises recessed surface portions contacting the protrusions.

13. The integrated circuit device of claim 12,

wherein the liner comprises an insulating liner and a stress liner that include different materials,

wherein the insulating liner contacts lower side walls of the fin-type active area and has a first upper surface at a first height from the substrate, and

wherein the stress liner is spaced apart from the lower side walls of the fin-type active area with the insulating liner between the stress liner and the lower side walls of the fin-type active area, and has a second upper surface at a second height from the substrate,

wherein the second height is higher than the first height.

14. The integrated circuit device of claim 13,

wherein the second upper surface of the stress liner faces the protrusions.

15. The integrated circuit device of claim 13,

wherein the substrate comprises a trench defining the fin-type active area,

wherein the insulating liner comprises a side wall extension between the fin-type active area and the stress liner in the trench and a bottom extension connected integrally to the side wall extension and between a bottom surface of the trench and the stress liner, and

wherein the side wall extension has a first thickness and the bottom extension has a second thickness, wherein the first thickness is greater than the second thickness.

16. The integrated circuit device of claim 13,

wherein the device isolation layer comprises an upper surface at a third height from the substrate, and

wherein the third height is lower than the first height.

17. The integrated circuit device of claim 12, wherein the device isolation layer comprises a concave upper surface facing away from the substrate.

18. The integrated circuit device of claim 12, wherein the device isolation layer comprises an inclined surface extending from the liner to a center portion in an upper surface of the device isolation layer, and

wherein a vertical distance between the substrate and the inclined surface decreases toward the center portion in the upper surface.

19. The integrated circuit device of claim 12, wherein the protrusions surround end portions of the liner.