Low power edge and data sampling

• US 10,708,036 B2
• Filed: 02/27/2018
• Issued: 07/07/2020
• Est. Priority Date: 04/30/2010
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L.
• Primary Examiner(s): Lugo, David B
• Application Number:
  US15/907,200
• Publication Number:
  US 20180287776A1
• Time in Patent Office: 861 Days
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0033 Correction by delay
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0332 with an integrator-detector

Abstract

An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

Claims

1. An integrated circuit receiver comprising:

a data receiving circuit responsive to a timing signal to detect a data signal level within a valid data region of a data signal, the data receiving circuit comprising a non-integrating sampler;

an edge receiving circuit including an integrating receiver to receive the data signal and generate an integrated output in response to the timing signal, the edge receiving circuit including a sampler to sample the integrated output to detect a signal level in a transition region of the data signal, the transition region at an end of the valid data range.

2. The integrated circuit receiver according to claim 1 wherein:

the data receiving circuit detects a data value in the valid data region of the data signal; and

the edge receiving circuit detects an edge value in the transition region of the data signal.

3. The integrated circuit receiver according to claim 1 wherein the timing signal includes a precharge interval and a sense interval and wherein:

the integrating receiver circuit includes a saturating integrator responsive to the precharge interval and a sampling receiver circuit coupled to the saturating integrator and responsive to the sense interval.

4. The integrated circuit receiver according to claim 1 wherein:

the timing signal accompanies the data signal in a quadrature relationship.

5. The integrated circuit receiver according to claim 3 and further including:

logic to selectively disable the saturating integrator.

6. The integrated circuit receiver according to claim 1 wherein the edge receiving circuit generates early/late information based on detecting a transition of the data signal, the early/late information for use by a timing control circuit to adjust the relative phases of the timing signal and the data symbol.

7. The integrated circuit receiver according to claim 6 wherein the timing control circuit is disposed in the integrated circuit receiver.

8. The integrated circuit receiver according to claim 1 wherein the timing signal accompanies the data signal in an in-phase relationship.

9. The integrated circuit receiver according to claim 1 wherein the timing signal comprises a clock signal.

10. The integrated circuit receiver according to claim 1 wherein the timing signal comprises a strobe signal.

11. A method of operation in an integrated circuit receiver, the method comprising:

receiving a data signal having a valid data region and a transition region;

receiving a timing signal created synchronous with the data signal;

detecting a data value in the valid data region in response to the timing signal in a non-integrating manner;

detecting an edge value in the transition region in response to the timing signal in an integrating manner to generate early/late information;

wherein detecting an edge value in the transition region comprises integrating the data signal in response to the timing signal to generate an integrated output and sampling the integrated output.

12. The method according to claim 11 wherein the data signal and the timing signal are received in a quadrature relationship, and wherein detecting an edge value in the transition region comprises:

integrating over an interval corresponding to respective precharge and sense portions of the timing signal;

generating the integrated output; and

sampling the integrated output to generate the early/late information.

13. The method according to claim 11 wherein detecting a data value in the valid data region comprises directly sampling the valid data region.

14. The method according to claim 11 wherein the timing signal comprises a clock signal.

15. The method according to claim 11 wherein the timing signal comprises a strobe signal.

16. A signaling system comprising:

a first integrated circuit device including a transmitter circuit to transmit a data signal and an accompanying timing signal, the timing signal created synchronous with the data signal;

a second integrated circuit device including a receiver circuit to receive the data signal and timing signal, the receiver circuit comprising

a non-integrating sampling receiver circuit responsive to a timing signal to detect a valid data region of a data signal; and

an integrating receiver circuit to receive the data signal and generate an integrated output in response to the timing signal, the integrating receiver circuit including a sampler to sample the integration output to detect a transition region associated with the data signal.

17. The signaling system according to claim 16 wherein the transmitter circuit transmits the timing signal and the data signal to the receiver circuit in quadrature, and wherein:

the integrating receiver circuit includes a saturating integrator responsive to a precharge interval of the timing signal and a third sampler circuit coupled to the integrator and responsive to a sense interval of the timing signal.

18. The signaling system according to claim 16 wherein the transmitter circuit transmits the timing and data signals in phase, and wherein:

the integrating receiver circuit includes a windowed integrator responsive to adjustable precharge and sense portions of the timing signal.

19. The signaling system according to claim 16 and further including:

a backchannel for communicating early/late information from the second integrated circuit to the first integrated circuit.

20. The signaling system according to claim 19 and further including:

timing control logic to adjust the relative phases of the timing signal and the data signal based on the early/late information.