System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects

• US 10,709,319 B2
• Filed: 04/17/2017
• Issued: 07/14/2020
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Original Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Inventors: Blanquart, Laurent
• Primary Examiner(s): Pyo, Kevin K
• Application Number:
  US15/489,588
• Publication Number:
  US 20170221945A1
• Time in Patent Office: 1,184 Days
• Field of Search: 2502081, 2502141
• CPC Class Codes: A61B 1/00009 of image signals during a use of endoscope
• CPC Class Codes: A61B 1/051 Details of CCD assembly
• CPC Class Codes: A61B 1/0676 at distal tip of an endoscope
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 31/028 : including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0296 : including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
• CPC Class Codes: H01L 31/0304 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H04N 23/555 : for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
• CPC Class Codes: H04N 23/56 : provided with illuminating means
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 : Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/772 : comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 : comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.

Claims

1. An imaging sensor comprising:

a pixel array comprising a plurality of pixel columns disposed on a first substrate, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;

a plurality of supporting circuits disposed on a second substrate and corresponding to each of the plurality of pixel sub-columns, wherein the plurality of supporting circuits disposed on the second substrate are each only connected to one of the plurality of pixel sub-columns; and

wherein the plurality of supporting circuits are configured to independently read and process data from a corresponding pixel sub-column, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.

2. The imaging sensor of claim 1, further comprising one or more additional substrates.

3. The imaging sensor of claim 2, wherein the one or more additional substrates are disposed remotely relative to the first substrate.

4. The imaging sensor of claim 2, further comprising a pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate and a circuit sub-column bus for each of the plurality of supporting circuits that correspond to each of the plurality of pixel sub-columns on the one or more additional substrates.

5. The imaging sensor of claim 4, wherein each pixel sub-column bus is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates, wherein the first substrate and the one or more additional substrates are in a stacked configuration.

6. The imaging sensor of claim 4, further comprising at least one interconnect connecting the pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate with a corresponding circuit sub-column bus for each of the plurality of supporting circuits on the one or more additional substrates.

7. The imaging sensor of claim 1, wherein the imaging sensor is backside illuminated.

8. The imaging sensor of claim 1, wherein each pixel sub-column is electronically isolated from other pixel sub-columns.

9. The imaging sensor of claim 1, wherein a dedicated portion of the plurality of supporting circuits are dedicated to a corresponding pixel sub-column of the pixel array.

10. The imaging sensor of claim 1, wherein reading pixel sub-columns within the same pixel column simultaneously comprises:

reading and processing data by supporting circuits corresponding to a specific pixel sub-column in parallel with supporting circuits corresponding to another pixel sub-column within the same pixel column.

11. An imaging sensor comprising:

a plurality of stacked substrates comprising a first substrate and one or more additional substrates proximal to the first substrate;

a pixel array on the first substrate comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;

a pixel sub-column bus on the first substrate for each of the plurality of pixel sub-columns;

a plurality of supporting circuits on the one or more additional substrates, the plurality of supporting circuits comprising a plurality of circuit columns corresponding to the plurality of pixel columns, wherein each of the plurality of circuit columns comprises a plurality of circuit sub-columns corresponding the plurality of pixel sub-columns, and, wherein the plurality of supporting circuits disposed on the one or more additional substrates are each only connected to one of the plurality of pixel sub-columns;

a circuit sub-column bus corresponding to each of the plurality of pixel sub-columns; and

a plurality of interconnects for electrically connecting a pixel sub-column bus with a corresponding circuit sub-column bus;

wherein the plurality of supporting circuits located on the one or more additional substrates that are proximal to the first substrate in each of the circuit sub-columns are configured to independently read and process data from corresponding pixel sub-columns, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.

12. The imaging sensor of claim 11, wherein each pixel sub-column bus is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates, wherein the first substrate and the one or more additional substrates are in a stacked configuration.

13. The imaging sensor of claim 11, wherein each pixel sub-column is electronically isolated from other pixel sub-columns.

14. The imaging sensor of claim 11, wherein supporting circuits within a specific circuit sub-column are dedicated to a corresponding to pixel sub-column of the pixel array.

15. The imaging sensor of claim 11, wherein reading pixel sub-columns within the same pixel column simultaneously comprises:

reading and processing data, by supporting circuits within a specific circuit sub-column, in parallel within supporting circuits located in circuit sub-columns within the same circuit column.

16. An imaging method comprising:

receiving and converting electromagnetic energy to data or data signals using a pixel array on a first substrate, the pixel array comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns; and

processing the data or data signals by a plurality of supporting circuits, wherein the plurality of supporting circuits are located on one or more additional substrates proximal to the first substrate, the plurality of supporting circuits comprising a plurality of circuit columns corresponding to and each connected only to one pixel column in the plurality of pixel columns, wherein each of the plurality of circuit columns comprises a plurality of circuit sub-columns corresponding the plurality of pixel sub-columns;

wherein the plurality of supporting circuits located on the one or more additional substrates that are proximal to the first substrate in each of the circuit sub-columns independently read and process data from a corresponding pixel sub-column, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.

17. The imaging method of claim 16, wherein reading and processing data from the pixel sub-columns comprises starting with a first pixel in each pixel sub-column within a same pixel column and sequentially reading pixel data from each subsequent pixel in the pixel sub-columns within the same pixel column a last pixel in each pixel sub-column within the pixel column is read.

18. The imaging method of claim 16, wherein the supporting circuits read the pixel data or signals via interconnects between pixel sub-columns and corresponding circuit sub-columns, wherein the data or signals from one pixel sub-column is processed by one circuit sub-column.

19. The imaging method of claim 16, further comprising processing the data or data signals into an image.

20. The imaging method of claim 16, wherein reading pixel sub-columns within the same pixel column simultaneously comprises:

reading and processing data, by supporting circuits within a specific circuit sub-column, in parallel within supporting circuits located in circuit sub-columns within the same circuit column.