Non-volatile storage system with dynamic allocation of applications to memory based on usage monitoring

• US 10,713,158 B2
• Filed: 06/28/2018
• Issued: 07/14/2020
• Est. Priority Date: 06/28/2018
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Neufeld, Nadav, Ng, Mei Yi Madeline, Levi, Enosh, Sela, Rotem
• Primary Examiner(s): Ruiz, Aracelis
• Application Number:
  US16/021,231
• Publication Number:
  US 20200004671A1
• Time in Patent Office: 747 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Technology is disclosed for dynamically assigning apps to non-volatile memory based on monitoring the apps'"'"' usage of memory resources. For a memory system having a high endurance section, such as binary (or single level cell, SLC) memory, and a lower endurance section, such as multi-level cell (MLC) memory, an app, including both the code for executing the app and the associated data payload, may initially be stored in the lower endurance section. The memory system monitors the activity of the app for high levels of activity and, if the app is being frequently written, the memory system notifies the host. In response, the host can request the memory system to move the app or just its associated payload to the high endurance section.

Claims

1. An apparatus, comprising:

a non-volatile memory having a first section and a second section, wherein the second section is configured to have a higher endurance level than the first section; and

one or more control circuits connected to the non-volatile memory, wherein the one or more control circuits are configured to;

receive an application from a host, the application including code for executing the application and data used by the application, and a range of logical addresses corresponding to the code for executing the application and data used by the application;

store the application in the first section of the non-volatile memory;

monitor a frequency of rewriting of the whole of the range of logical addresses corresponding to the code for executing the application and the data used by the application;

in response to the frequency of rewriting of the whole of the range of logical addresses corresponding to the code for executing the application and the data used by the application exceeding a first value, send a first notification to the host; and

in response to receiving a reply to the first notification from the host requesting that the data used by the application be transferred from the first section of the non-volatile memory to the second section of the non-volatile memory, transfer storage of the whole of the range of logical addresses corresponding to data used by the application from the first section of the non-volatile memory to the second section of the non-volatile memory.

2. The apparatus of claim 1, wherein the one or more control circuits are further configured to:

subsequent to transferring storage of the data used by the application to the second section of the non-volatile memory, monitor the frequency of rewriting of the data used by the application;

in response to the frequency of rewriting of the data used by the application being lower than a second value, send a notification to the host; and

in response to a reply from the host requesting that the data used by the application be transferred from the second section of the non-volatile memory to the first section of the non-volatile memory, transfer storage of the data used by the application from the second section of the non-volatile memory to the first section of the non-volatile memory.

3. The apparatus of claim 1, wherein, when the one or more control circuits receive the application from the host, the one or more control circuits also receive a request from the host that specifies that the application is to be stored in the first section.

4. The apparatus of claim 1, wherein the one or more control circuits are further configured to reconfigure the memory sections to reassign a portion of one of the first section or the second section to the other one of the first section or the second section.

5. The apparatus of claim 1, wherein the one or more control circuits are further configured to transfer storage of the code for executing the application from the first section of the non-volatile memory to the second section of the non-volatile memory in response to the reply from the host further requesting that the code for executing the application be transferred.

6. The apparatus of claim 1, wherein the one or more control circuits are further configured to transfer storage of data used by an associated application from the first section of the non-volatile memory to the second section of the non-volatile memory in response to the reply from the host further requesting that the data used by the associated application be transferred.

7. The apparatus of claim 1, wherein:

the first section comprises multi-level memory cells; and

the second section comprises single level memory cells.

8. The apparatus of claim 1, wherein the one or more control circuits are further configured to:

monitor a frequency of rewriting of individual logical block addresses of the range of logical addresses corresponding to the code for executing the application and the data used by the application;

in response to the frequency of rewriting of one or more of the individual logical addresses of the range of logical addresses exceeding an individual logical block address threshold, send a second notification to the host; and

in response to receiving a reply to the second notification from the host requesting that the one or more of the individual logical addresses of the range of logical addresses exceeding the individual logical block address threshold be transferred from the first section of the non-volatile memory to the second section of the non-volatile memory, transfer storage of the one or more of the individual logical addresses of the range of logical addresses exceeding the individual logical block address threshold to the second section of the non-volatile memory.

9. A method, comprising:

storing an application in a range of logical addresses in a first section of a non-volatile memory system, the first section being one of a section of high endurance memory cells or a section of high density memory cells of which the non-volatile memory system is comprised, and where the application includes code for executing the application and a data payload of the application;

monitoring a frequency of rewriting of the whole of the range of logical addresses corresponding to the code for executing the application and the data payload caused by the application;

in response to a comparison of the frequency of rewriting of the whole of the range of logical addresses corresponding to the code for executing the application and the data payload to a first threshold, issuing by the non-volatile memory system a first alert to a host;

receiving from the host a reply to the first alert instructing the non-volatile memory system to relocate the data payload from the first section of the non-volatile memory system to a second section of the non-volatile memory system; and

in response to the reply to the first alert, relocating the whole of the range of logical addresses corresponding to the data payload of the application to the second section of the non-volatile memory system.

10. The method of claim 9, further comprising:

prior to monitoring the frequency of rewriting the first section, receiving at the non-volatile memory system from the host the application and a specification of the range of logical addresses in the first section of the non-volatile memory system for storing of the application, wherein the storing the application in the first section of the non-volatile memory system is in response to the specification.

11. The method of claim 9, further comprising:

subsequent to relocating the data payload to the second section, monitoring a frequency rewriting of the second section caused by the application;

in response to a comparison of the frequency rewriting to a second threshold, issuing a further alert to the host by the non-volatile memory system;

in response to the further alert, receiving a reply at the non-volatile memory system from the host to relocate the data payload from the second section of the non-volatile memory system to the first section of the non-volatile memory system; and

relocating the data payload from the second section to the first section of the non-volatile memory system.

12. The method of claim 9, further comprising:

in response to the reply, relocating the code for executing the application to the second section of the non-volatile memory system.

13. The method of claim 9, further comprising:

monitoring a rate of aging for the section of high endurance memory cells;

monitoring a rate of aging for the section of high density memory cells; and

in response to an imbalance between the rate of aging for the section of high endurance memory cells and the rate of aging for the section of high density memory cells, reassigning memory cells from one of the section of high endurance memory cells or the section of high density memory cells to the other of the section of high endurance memory cells or the section of high density memory cells.

14. The method of claim 13, wherein the reassigning is performed in response to a host request.

15. The method of claim 9, further comprising:

monitoring a frequency of rewriting of individual logical block addresses of the range of logical addresses corresponding to the code for executing the application and the data payload;

in response to the frequency of rewriting of one or more of the individual logical addresses of the range of logical addresses exceeding an individual logical block address threshold, issuing a second alert to the host;

receiving from the host a reply to the second alert instructing the non-volatile memory system to relocate the data payload from the first section of the non-volatile memory system to a second section of the non-volatile memory system; and

in response to the reply to the second alert, relocating the whole of the range of logical addresses corresponding to the data payload of the application to the second section of the non-volatile memory system.

16. An apparatus, comprising:

a non-volatile memory having a first section and a second section, wherein the second section is configured to have a higher endurance level than the first section; and

means for receiving an application from a host, the application including code for executing the application and data used by the application, and a range of logical block addresses corresponding to the code for executing the application and the data used by the application;

means for storing the application in the first section of the non-volatile memory;

means for monitoring a frequency of rewriting of individual logical block addresses of the range of logical block addresses corresponding to the code for executing the application and the data used by the application;

means for sending a first notification to the host in response to the frequency of rewriting of the individual logical block addresses of the range of logical block addresses corresponding to the code for executing the application and the data used by the application exceeding a first value; and

means for transferring storage of the whole of the range of logical block addresses corresponding to data used by the application from the first section of the non-volatile memory to the second section of the non-volatile memory in response to receiving a reply to the first notification from the host requesting that the data used by the application be transferred from the first section of the non-volatile memory to the second section of the non-volatile memory.

17. The apparatus of claim 16, wherein, when the means for receiving the application receives the application from the host, the means for receiving the application also receives a request from the host that specifies that the application is to be stored in the first section.

18. The apparatus of claim 16, further comprising:

means for reconfiguring the memory sections to reassign a portion of one of the first section or the second section to the other one of the first section or the second section.

19. The apparatus of claim 16, further comprising:

means for transferring storage of the code for executing the application from the first section of the non-volatile memory to the second section of the non-volatile memory in response to the reply from the host further requesting that the code for executing the application be transferred.

20. The apparatus of claim 16, further comprising:

means for transferring storage of data used by an associated application from the first section of the non-volatile memory to the second section of the non-volatile memory in response to the reply from the host further requesting that the data used by the associated application be transferred.