Semiconductor defect classification device, method for classifying defect of semiconductor, and semiconductor defect classification system

• US 10,713,778 B2
• Filed: 07/11/2018
• Issued: 07/14/2020
• Est. Priority Date: 12/19/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Namyeong, Kang, Hyohyeong, Kim, Yongdeok
• Primary Examiner(s): Mariam, Daniel G
• Application Number:
  US16/032,356
• Publication Number:
  US 20190188840A1
• Time in Patent Office: 734 Days
• Field of Search: 382149
• CPC Class Codes: G01N 2021/8854 Grading and classifying of flaws
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G06F 18/2413 based on distances to training or reference patterns
• CPC Class Codes: G06N 20/10 using kernel methods, e.g. support vector machines [SVM]
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 5/01 Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
• CPC Class Codes: G06T 2207/10056 Microscopic image
• CPC Class Codes: G06T 2207/10061 from scanning electron microscope
• CPC Class Codes: G06T 2207/20072 Graph-based image processing
• CPC Class Codes: G06T 2207/20076 Probabilistic image processing
• CPC Class Codes: G06T 2207/20081 Training; Learning
• CPC Class Codes: G06T 2207/20084 Artificial neural networks [ANN]
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06V 10/764 using classification, e.g. of video objects
• CPC Class Codes: G06V 10/7788 the supervisor being a human, e.g. interactive learning with a human teacher
• CPC Class Codes: G06V 10/82 using neural networks
• CPC Class Codes: G06V 2201/06 : Recognition of objects for industrial automation
• CPC Class Codes: H01L 21/67288 : Monitoring of warpage, curvature, damage, defects or the like
• CPC Class Codes: H01L 22/12 : for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 : Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A semiconductor defect classification device includes feature extractors that are configured to receive images of semiconductor patterns on a wafer and to extract features of the images from the images, and a classifier that is configured to receive the features of the images and first meta information about the wafer and to use machine learning to classify a defect of the semiconductor patterns associated with the images based on the features of the images and the first meta information.

Claims

1. A semiconductor defect classification device comprising:

feature extractors configured to receive images of semiconductor patterns on a wafer, the images comprising a low resolution image, a high resolution image, a reference image, and an optical image of the semiconductor patterns, and to extract features of the images from the images;

a comparator configured to compare a feature of the low resolution image and a feature of the reference image and to generate a result of the comparison; and

a classifier configured to receive the features of the images, first meta information about the wafer, and the result of the comparison and to use machine learning to classify a defect of the semiconductor patterns associated with the images based on the features of the images, which include the feature of the low resolution image, a feature of the high resolution image, and a feature of the optical image, the result of the comparison, and the first meta information.

2. The semiconductor defect classification device of claim 1, wherein the feature extractors are configured to extract the features of the images by using a stacked convolutional neural network (CNN).

3. The semiconductor defect classification device of claim 1, wherein the classifier is further configured to classify the defect of the semiconductor patterns by using one of a decision tree, a neural network, and a support vector machine.

4. The semiconductor defect classification device of claim 1, wherein the first meta information comprises at least one of information about a type of a manufacture device processing the wafer, information about a type of a semiconductor device that is manufactured by processing the wafer, information about a type of a process used by the manufacture device to process the wafer, and information about a process operation that the manufacture device performs with respect to the wafer.

5. The semiconductor defect classification device of claim 1, wherein the classifier is further configured to receive second meta information associated with an imaging device used for taking the images of the semiconductor patterns;

and

wherein the classifier is further configured to use the second meta information to classify the defect.

6. The semiconductor defect classification device of claim 5, wherein the second meta information comprises at least one of information about a type of the imaging device used for taking the images of the semiconductor patterns, information about positioning of the imaging device for taking the images, and information about location of the semiconductor patterns on the wafer;

wherein the information about positioning of the imaging device comprises distance information, location information, and/or angle information associated with the imaging device.

7. The semiconductor defect classification device of claim 1, wherein the classifier is further configured to use third meta information associated with the machine learning to classify the defect.

8. The semiconductor defect classification device of claim 7, wherein the third meta information comprises information about a creator that generates learning data used by the classifier as part of the machine learning.

9. The semiconductor defect classification device of claim 1,

wherein the semiconductor defect classification device further comprises:

an offset align device configured to compare the feature of the low resolution image and the feature of the reference image to detect an offset between the feature of the low resolution image and the feature of the reference image and to generate an aligned low resolution image and an aligned reference image by using the offset.

10. The semiconductor defect classification device of claim 9,

wherein the classifier is further configured to classify the defect of the semiconductor patterns based on the aligned low resolution image and the aligned reference image.

11. The semiconductor defect classification device of claim 1, further comprising:

a similarity classification device configured to compare the images and previous images stored in a database and to classify a similarity of the images and the previous images stored in the database,

wherein, the images are stored in the database as a part of the previous images when the similarity is lower than a threshold value.

12. The semiconductor defect classification device of claim 11, wherein at least one of the feature extractors and the classifier perform additional machine learning based on the previous images stored in the database when a learning condition is satisfied.

13. The semiconductor defect classification device of claim 1, further comprising:

a rejection device configured to receive a result of a classification of the defect by the classifier, to determine a reliability of the result of the classification, and to provide notification that the reliability of the result of the classification is low when the reliability of the result of the classifications lower than a threshold value.

14. A method of classifying a semiconductor defect, the method comprising:

receiving images of semiconductor patterns on a wafer, the images comprising a low resolution image and a reference image of the semiconductor patterns;

extracting features of the images from the images;

receiving meta information associated with the images; and

using machine learning to classify a defect of the semiconductor patterns based on the features and the meta information;

wherein the extracting of the features of the images comprises;

extracting a first feature of the low resolution image and a second feature of the reference image, respectively;

comparing the first feature and the second feature to detect an offset between the low resolution image and the reference image;

generating an aligned low resolution image and an aligned reference image from the low resolution image and the reference image based on the offset; and

comparing the aligned low resolution image and the aligned reference image to extract a comparison feature.

15. A semiconductor defect classification system comprising:

a manufacture device configured to generate semiconductor patterns in a wafer;

an imaging device configured to generate images of the semiconductor patterns, the images comprising a low resolution image, a high resolution image, a reference image, and an optical image of the semiconductor patterns;

a semiconductor defect classification device configured to perform defect classification on the images generated by the imaging device;

wherein the semiconductor defect classification device comprises;

feature extractors configured to receive the images of semiconductor patterns and to extract features of the images from the images, the images comprising a low resolution image and a reference image of the semiconductor patterns;

an offset align device configured to compare a feature of the low resolution image and a feature of the reference image to detect an offset between the feature of the low resolution image and the feature of the reference image and to generate an aligned low resolution image and an aligned reference image by using the offset; and

a classifier configured to receive the features of the images and first meta information about the wafer and to use machine learning to classify a defect of the semiconductor patterns associated with the images based on the aligned low resolution image, the aligned reference image, and the first meta information.

16. The semiconductor defect classification system of claim 15, wherein the manufacture device is further configured to output the first meta information associated with the semiconductor patterns,

wherein the imaging device is further configured to output second meta information associated with the imaging device, and

wherein semiconductor defect classification device is further configured to perform the defect classification on the images by using the aligned low resolution image, the aligned reference image, the first meta information, the second meta information, and third meta information.