Bi-sided pattern processor

• US 10,714,172 B2
• Filed: 01/16/2019
• Issued: 07/14/2020
• Est. Priority Date: 09/21/2017
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/248,933
• Publication Number:
  US 20190180815A1
• Time in Patent Office: 545 Days
• Field of Search: 365 94-105
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H10B 20/27 ROM only

Abstract

A bi-sided pattern processor comprises a plurality of storage-processing units (SPU'"'"'s). Each of the SPU'"'"'s comprises at least a memory array and a pattern-processing circuit. The preferred pattern processor further comprises a semiconductor substrate with opposing first and second surfaces. The memory array is disposed on the first surface, whereas the pattern-processing circuit is disposed on the second surface. The memory array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of inter-surface connections.

Claims

1. A bi-sided pattern processor, comprising:

an input for transferring at least a first portion of a first pattern;

a plurality of storage-processing units (SPU'"'"'s) communicatively coupled with said input, each of said SPU'"'"'s comprising at least a memory array and a pattern-processing circuit, wherein said memory array stores at least a second portion of a second pattern, said pattern-processing circuit performs pattern processing for said first and second patterns;

a semiconductor substrate with first and second surfaces, wherein said memory array is disposed on said first surface, said pattern-processing circuit is disposed on said second surface, said memory array and said pattern-processing circuit are communicatively coupled by a plurality of inter-surface connections.

2. The pattern processor according to claim 1, wherein said memory array includes a RAM array.

3. The pattern processor according to claim 2, wherein said RAM array is a SRAM array or DRAM array.

4. The pattern processor according to claim 1, wherein said memory array includes a ROM array.

5. The pattern processor according to claim 4, wherein said ROM array is a mask-ROM array, an OTP array, an EPROM array, an EEPROM array, a flash array, or a 3-D memory (3D-M) array.

6. The pattern processor according to claim 1, wherein the projection of said memory array on said second surface at least partially overlaps said pattern-processing circuit.

7. The pattern processor according to claim 1, wherein each memory array is vertically aligned and communicatively coupled with a pattern-processing circuit.

8. The pattern processor according to claim 1, wherein each pattern-processing circuit is vertically aligned and communicatively coupled with at least a memory array.

9. The pattern processor according to claim 1, the pitch of said pattern-processing circuit is an integer multiple of the pitch of said memory array.

10. The pattern processor according to claim 1, said inter-surface connections are through-silicon vias (TSV'"'"'s).

11. The pattern processor according to claim 1 being a bi-sided processor with an embedded search-pattern library, wherein said first pattern includes a target pattern and said second pattern includes a search pattern.

12. The pattern processor according to claim 1 being a bi-sided information-security processor, wherein said input transfers at least a portion of data from a network packet or a computer file;

said memory array stores at least a portion of a virus pattern; and

, said pattern-processing circuit is a code-matching circuit for searching said virus pattern in said portion of data.

13. The pattern processor according to claim 1 being a bi-sided data-analysis processor, wherein said input transfers at least a portion of data from a big-data database;

said memory array stores at least a portion of a keyword; and

, said pattern-processing circuit is a string-matching circuit for searching said keyword in said portion of data.

14. The pattern processor according to claim 1 being a bi-sided speech-recognition processor, wherein said input transfers at least a portion of audio data;

said memory array stores at least a portion of an acoustic/language model; and

, said pattern-processing circuit is a speech-recognition circuit for performing speech recognition on said portion of audio data with said acoustic/language model.

15. The pattern processor according to claim 1 being a bi-sided image-recognition processor, wherein said input transfers at least a portion of image data;

said memory array stores at least a portion of an image model; and

, said pattern-processing circuit is an image-recognition circuit for performing image recognition on said portion of image data with said image model.

16. The pattern processor according to claim 1 being a bi-sided storage with in-situ pattern-processing capabilities, wherein said first pattern is a search pattern and said second pattern is a target pattern.

17. The pattern processor according to claim 1 being a bi-sided anti-virus storage, wherein said input transfers at least a portion of a virus pattern;

said memory array stores at least a portion of data from a computer file; and

, said pattern-processing circuit is a code-matching circuit for searching said virus pattern in said portion of data.

18. The pattern processor according to claim 1 being a bi-sided searchable storage, wherein said input transfers at least a portion of a keyword;

said memory array stores at least a portion of data from a big-data database; and

, said pattern-processing circuit is a string-matching circuit for searching said keyword in said portion of data.

19. The pattern processor according to claim 1 being a bi-sided searchable audio storage, wherein said input transfers at least a portion of an acoustic/language model;

said memory array stores at least a portion of audio data; and

, said pattern-processing circuit is a speech-recognition circuit for performing speech recognition on said portion of audio data with said acoustic/language model.

20. The pattern processor according to claim 1 being a bi-sided searchable image storage, wherein said input transfers at least a portion of an image model;

said memory array stores at least a portion of image data; and

, said pattern-processing circuit is an image-recognition circuit for performing image recognition on said portion of image data with said image model.