Hybrid memory devices

• US 10,714,179 B2
• Filed: 10/07/2016
• Issued: 07/14/2020
• Est. Priority Date: 10/07/2016
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ge, Ning, Simske, Steven J, George, David
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US16/323,072
• Publication Number:
  US 20190221261A1
• Time in Patent Office: 1,376 Days
• Field of Search: 365148, 365178
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

In some examples, a hybrid memory device includes multiple memory cells, where a given memory cell of the multiple memory cells includes a volatile memory element having a plurality of layers including electrically conductive layers and a dielectric layer between the electrically conductive layers, and a non-volatile resistive memory element to store different data states represented by respective different resistances of the non-volatile resistive memory element, the non-volatile resistive memory element having a plurality of layers including electrically conductive layers and a resistive switching layer between the electrically conductive layers of the non-volatile resistive memory element.

Claims

1. A hybrid memory device comprising:

a plurality of memory cells, wherein a given memory cell of the plurality of memory cells comprises;

a volatile memory element comprising a plurality of layers including electrically conductive layers and a dielectric layer between the electrically conductive layers; and

a non-volatile resistive memory element to store different data states represented by respective different resistances of the non-volatile resistive memory element, the non-volatile resistive memory element comprising a plurality of layers including electrically conductive layers and a resistive switching layer between the electrically conductive layers of the non-volatile resistive memory element;

a volatile memory access controller to access volatile memory elements of the plurality of memory cells; and

a non-volatile memory access controller to access non-volatile resistive memory elements of the plurality of memory cells.

2. The hybrid memory device of claim 1, wherein the volatile memory element and the non-volatile resistive memory element of the given memory cell share a common electrically conductive layer.

3. The hybrid memory device of claim 1, wherein the plurality of layers of the volatile memory element form a dynamic random access memory (DRAM) storage capacitor, the plurality of layers of the volatile memory element comprising a first electrically conductive layer, the dielectric layer, and a second electrically conductive layer.

4. The hybrid memory device of claim 3, wherein the plurality of layers of the non-volatile resistive memory element comprise the first electrically conductive layer, the resistive switching layer, and a third electrically conductive layer.

5. The hybrid memory device of claim 4, wherein the first electrically conductive layer, the dielectric layer, the second electrically conductive layer, the resistive switching layer, and the third electrically conductive layer are arranged in a stack of layers.

6. The hybrid memory device of claim 1, wherein the given memory cell further comprises:

a transistor activatable to access the given memory cell.

7. The hybrid memory device of claim 1, wherein the non-volatile memory access controller is to read the non-volatile resistive memory element of the given memory cell by using an alternating current (AC) read signal to sense a resistance of the non-volatile resistive memory element of the given memory cell.

8. The hybrid memory device of claim 7, herein the non-volatile memory access controller is to write the non-volatile resistive memory element of the given memory cell by using a direct current bias voltage to program a resistance of the non-volatile resistive memory element of the given memory cell.

9. The hybrid memory device of claim 1, wherein the non-volatile resistive memory element and the volatile memory element of the given memory cell are arranged in series.

10. The hybrid memory device of claim 1, wherein the non-volatile resistive memory element and the volatile memory element of the given memory cell are arranged in parallel.

11. An electronic device comprising:

a processor; and

a hybrid memory device accessible by the processor, the hybrid memory device comprising;

a plurality of memory cells, wherein a given memory cell of the plurality of memory cells comprises;

a storage capacitor formed with a first electrically conductive layer, a dielectric layer, and a second electrically conductive layer; and

a memristor element formed with the first electrically conductive layer, a resistive switching layer, and a third electrically conductive layer.

12. The electronic device of claim 11, wherein the given memory cell further comprises a transistor activatable to access the given memory cell, the hybrid memory device further comprising:

a first access controller to access the storage capacitor of the given memory cell through the transistor; and

a second access controller to access the memristor element of the given memory cell through the transistor.

15. The electronic device of claim 11, wherein the first electrically conductive layer, the dielectric layer, the second electrically conductive layer, the resistive switching layer, and the third electrically conductive layer are arranged as a vertical stack of layers.

16. The electronic device of claim 11, wherein the resistive switching layer comprises an oxide-containing material.

17. The electronic device of claim 12, wherein the second access controller is to write the memristor element of the given memory cell by using a direct current bias voltage to program a resistance of the memristor element of the given memory cell.

18. The electronic device of claim 17, wherein the second access controller is to read the memristor element of the given memory cell by using an alternating current (AC) read signal to sense a resistance of the memristor element of the given memory cell.

13. A method of forming a hybrid memory device, comprising:

forming a first plurality of layers on a substrate to form a dynamic random access memory storage capacitor of a memory cell of the hybrid memory device, the first plurality of layers comprising electrically conductive layers and a dielectric conductive layer between the electrically conductive layers; and

forming a second plurality of layers on the substrate to form a non-volatile resistive memory element of the memory cell, the second plurality of layers comprising electrically conductive layers and a resistive switching layer between the electrically conductive layers of the non-volatile resistive memory element, wherein an electrically conductive layer of the non-volatile resistive memory element is electrically connected to an electrically conductive layer of the dynamic random access memory storage capacitor.

14. The method of claim 13, wherein the first plurality of layers and the second plurality of layers are formed on a region of the substrate that corresponds to the memory cell.

19. The method of claim 13, wherein the electrically conductive layer of the non-volatile resistive memory element and the electrically conductive layer of the dynamic random access memory storage capacitor that are electrically connected are part of a common electrically conductive layer.