Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures

• US 10,714,350 B2
• Filed: 10/26/2017
• Issued: 07/14/2020
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holdings B.V.
• Inventors: Chen, Jerry Peijun, Alokozai, Fred
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US15/795,056
• Publication Number:
  US 20180158688A1
• Time in Patent Office: 992 Days
• Field of Search: 257300
• CPC Class Codes: C23C 16/34 Nitrides C23C16/303 takes precedence
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 2924/01041 Niobium [Nb]
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/033 : the capacitor extending over the transistor

Abstract

Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures are provided. In some embodiments methods may include contacting a substrate with a first reactant comprising a transition metal precursor, contacting the substrate with a second reactant comprising a niobium precursor and contacting the substrate with a third reactant comprising a nitrogen precursor. In some embodiments related semiconductor device structures may include a semiconductor body and an electrode comprising a transition metal niobium nitride disposed over the semiconductor body.

Claims

1. A semiconductor device structure comprising:

a semiconductor body;

a gate dielectric overlying and in contact with the semiconductor body; and

an electrode disposed over the gate dielectric;

wherein the electrode comprises a bilayer comprising a first layer comprising a transition metal niobium nitride that comprises a transition metal and niobium and a second layer, adjacent to and overlying the first layer, comprising a metal nitride that comprises the transition metal, wherein the transition metal is provided in the first and second layers of the electrode.

2. The semiconductor device structure of claim 1, wherein the first layer comprises at least one of a tantalum niobium nitride and a tungsten niobium nitride.

3. The semiconductor device structure of claim 1, wherein the first layer has a Young'"'"'s modulus of greater than approximately 390 gigapascals.

4. The semiconductor device structure of claim 1, wherein the first layer has a density greater than approximately 5.4 g/cm³.

5. The semiconductor device structure of claim 1, wherein the first layer has an electrical resistivity of less than 1000μ

Ω

-cm.

6. A PMOS transistor comprising the semiconductor device structure of claim 1.

7. A dynamic random access (DRAM) capacitor comprising the semiconductor device structure of claim 1.

8. The semiconductor device structure of claim 1, wherein the first layer comprises a nanolaminate structure.

9. The semiconductor device structure of claim 1, wherein the transition metal comprises at least one of titanium, tungsten, and tantalum.

10. The semiconductor device structure of claim 1, wherein the electrode comprises a barrier material composed of a transition metal niobium nitride.

11. The semiconductor device structure of claim 1, wherein the electrode comprises a capping layer composed of a transition metal niobium nitride.

12. The semiconductor device structure of claim 1, wherein the electrode comprises a cylinder-type storage node.

13. The semiconductor device structure of claim 1, wherein the first layer is not a nanolaminate structure.

14. The semiconductor device structure of claim 1, wherein an etch selectively, defined as an etchable rate of the second layer relative to the first layer, is greater than 2:

1.

15. The semiconductor device structure of claim 1, wherein an etch selectively, defined as an etchable rate of the second layer relative to the first layer, is greater than 5:

1.

16. The semiconductor device structure of claim 1, wherein an etch selectively, defined as an etchable rate of the second layer relative to the first layer, is greater than 10:

1.

17. The semiconductor device structure of claim 1, wherein a thickness of at least one of the first layer and second layer varies across a surface of the semiconductor body.

18. A semiconductor device structure comprising:

a semiconductor body;

a gate dielectric overlying and in contact with the semiconductor body; and

a plurality of electrodes disposed over the gate dielectric at a plurality of locations, each electrode of the plurality of electrodes comprising a transition metal niobium nitride disposed over the gate dielectric;

wherein each electrode of the plurality of electrodes comprises a bilayer comprising a first layer comprising the transition metal niobium nitride and a second layer, adjacent to and overlying the first layer, comprising a metal nitride;

wherein a thickness of the first layer and the second layer of the bilayer of the plurality of electrodes differs at two or more of the plurality of locations such that two or more of the plurality of electrodes have different effective work functions.

19. A semiconductor device structure comprising:

a semiconductor body; and

an electrode comprising a transition metal niobium nitride disposed over the semiconductor body,

wherein the transition metal niobium nitride comprises at least one of a tantalum niobium nitride and a tungsten niobium nitride,

wherein the transition metal niobium nitride has a Young'"'"'s modulus of greater than approximately 390 gigapascals,

wherein the transition metal niobium nitride has a density greater than approximately 5.4 g/cm³, and

wherein the transition metal niobium nitride has an electrical resistivity of less than 1000μ

Ω

-cm.

20. A PMOS transistor or a dynamic random access (DRAM) capacitor comprising the semiconductor device structure of claim 19.