Semiconductor device and manufacturing method thereof

• US 10,714,358 B2
• Filed: 11/21/2019
• Issued: 07/14/2020
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakata, Junichiro, Ohara, Hiroki
• Primary Examiner(s): Coleman, William
• Application Number:
  US16/690,924
• Publication Number:
  US 20200090950A1
• Time in Patent Office: 236 Days
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming an oxide semiconductor layer containing indium by sputtering method;

forming a conductive film comprising a region in contact with the oxide semiconductor layer; and

etching the conductive film for forming a source electrode and a drain electrode and etching a region of the oxide semiconductor layer which is not covered by the source electrode or the drain electrode,

wherein the oxide semiconductor layer comprises a region in which a c-axis of a crystal is aligned along a direction perpendicular to a surface of the oxide semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein the oxide semiconductor layer further comprises gallium and zinc.

3. A method for manufacturing a semiconductor device comprising:

forming an oxide semiconductor layer containing indium by sputtering method;

forming a conductive film comprising a region in contact with the oxide semiconductor layer; and

etching the conductive film for forming a source electrode and a drain electrode and etching a region of the oxide semiconductor layer which is not covered by the source electrode or the drain electrode,

wherein the oxide semiconductor layer comprises a first region in which a c-axis of a crystal is aligned along a direction perpendicular to a surface of the oxide semiconductor layer and a second region containing a microcrystal is under the first region.

4. The method for manufacturing a semiconductor device according to claim 3,

wherein the oxide semiconductor layer further comprises gallium and zinc.

5. The method for manufacturing a semiconductor device according to claim 3,

wherein the first region is partially thinned in the step of etching the region of the oxide semiconductor layer.

6. A method for manufacturing a semiconductor device comprising:

forming an oxide semiconductor layer containing indium by sputtering method, the oxide semiconductor layer comprising a first region and a second region under the first region;

forming a conductive film comprising a region in contact with the oxide semiconductor layer; and

etching the conductive film for forming a source electrode and a drain electrode and etching a region of the first region of the oxide semiconductor layer which is not covered by the source electrode or the drain electrode,

wherein a c-axis of a crystal is aligned along a direction perpendicular to a surface of the oxide semiconductor layer in the first region, and

wherein the second region containing a microcrystal is under the first region.

7. The method for manufacturing a semiconductor device according to claim 6,

wherein the oxide semiconductor layer further comprises gallium and zinc.

8. The method for manufacturing a semiconductor device according to claim 6,

wherein the first region is partially thinned in the step of etching the region of the first region of the oxide semiconductor layer.