Display device including transistor and manufacturing method thereof

• US 10,714,503 B2
• Filed: 02/07/2019
• Issued: 07/14/2020
• Est. Priority Date: 07/03/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Sasaki, Toshinari, Hosoba, Miyuki
• Primary Examiner(s): Tran, Thanh Y.
• Application Number:
  US16/270,079
• Publication Number:
  US 20190172849A1
• Time in Patent Office: 523 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Claims

1. A semiconductor device comprising:

a first gate electrode;

a first insulating layer over the first gate electrode;

an oxide semiconductor layer over the first insulating layer;

a source electrode electrically connected to the oxide semiconductor layer;

a drain electrode electrically connected to the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer; and

a second gate electrode over the second insulating layer,

wherein the first insulating layer comprises silicon oxide and a region in contact with the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the second insulating layer comprises silicon oxide and a region in contact with the oxide semiconductor layer,

wherein the source electrode comprises a region overlapping with the first gate electrode,

wherein the drain electrode comprises a region overlapping with the first gate electrode,

wherein in a channel length direction of the oxide semiconductor layer, the second gate electrode is smaller than the oxide semiconductor layer, and

wherein a side surface of the oxide semiconductor layer comprises a region which is not covered with the source electrode or the drain electrode.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a microcrystalline region.

3. The semiconductor device according to claim 1, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode.

4. The semiconductor device according to claim 3, wherein the pixel electrode comprises indium tin oxide.

5. A semiconductor device comprising:

a first gate electrode;

a first insulating layer over the first gate electrode;

an oxide semiconductor layer over the first insulating layer;

a source electrode electrically connected to the oxide semiconductor layer;

a drain electrode electrically connected to the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer; and

a second gate electrode over the second insulating layer,

wherein the first insulating layer comprises silicon oxide and a region in contact with the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the second insulating layer comprises silicon oxide and a region in contact with the oxide semiconductor layer,

wherein the source electrode comprises titanium and a region overlapping with the first gate electrode,

wherein the drain electrode comprises titanium and a region overlapping with the first gate electrode,

wherein in a channel length direction of the oxide semiconductor layer, the second gate electrode is smaller than the oxide semiconductor layer, and

wherein a side surface of the oxide semiconductor layer comprises a region which is not covered with the source electrode or the drain electrode.

6. The semiconductor device according to claim 5, wherein the oxide semiconductor layer comprises a microcrystalline region.

7. The semiconductor device according to claim 5, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode.

8. The semiconductor device according to claim 7, wherein the pixel electrode comprises indium tin oxide.

9. A semiconductor device comprising:

a pixel portion and a driver circuit portion over a substrate,

wherein the pixel portion comprises a first transistor, a second transistor, a capacitor, and a light-emitting element,

wherein the driver circuit portion comprises a third transistor,

wherein the first transistor comprises a first gate electrode, a first insulating layer over the first gate electrode, a first oxide semiconductor layer over the first insulating layer, a source electrode electrically connected to the first oxide semiconductor layer and comprising a region in contact with a top surface of the first oxide semiconductor layer, a drain electrode electrically connected to the first oxide semiconductor layer and comprising a region in contact with the top surface of the first oxide semiconductor layer, a second insulating layer over the first oxide semiconductor layer, and a second gate electrode over the second insulating layer,

wherein the first gate electrode is electrically connected to the second transistor and one of electrodes of the capacitor,

wherein one of the source electrode and the drain electrode is electrically connected to the other of the electrodes of the capacitor,

wherein the other of the source electrode and the drain electrode is electrically connected to the light-emitting element,

wherein the second transistor comprises a second oxide semiconductor layer,

wherein the third transistor comprises a third semiconductor layer,

wherein the first insulating layer comprises silicon oxide and a region in contact with the first oxide semiconductor layer,

wherein the second insulating layer comprises silicon oxide and a region in contact with the first oxide semiconductor layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc,

wherein in a channel length direction of the first oxide semiconductor layer, the first gate electrode is larger than the first oxide semiconductor layer, and the second gate electrode is smaller than the first oxide semiconductor layer, and

wherein a side surface of the first oxide semiconductor layer comprises a region which is not covered with the source electrode or the drain electrode.

10. The semiconductor device according to claim 9, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode.

11. The semiconductor device according to claim 10, wherein the pixel electrode comprises indium tin oxide.

12. A semiconductor device comprising:

a pixel portion and a driver circuit portion over a substrate,

wherein the pixel portion comprises a first transistor, a second transistor, a capacitor, and a light-emitting element,

wherein the driver circuit portion comprises a third transistor,

wherein the first transistor comprises a first gate electrode, a first insulating layer over the first gate electrode, a first oxide semiconductor layer over the first insulating layer, a source electrode electrically connected to the first oxide semiconductor layer and comprising a region in contact with a top surface of the first oxide semiconductor layer, a drain electrode electrically connected to the first oxide semiconductor layer and comprising a region in contact with the top surface of the first oxide semiconductor layer, a second insulating layer over the first oxide semiconductor layer, and a second gate electrode over the second insulating layer,

wherein the first gate electrode is electrically connected to the second transistor and one of electrodes of the capacitor,

wherein one of the source electrode and the drain electrode is electrically connected to the other of the electrodes of the capacitor,

wherein the other of the source electrode and the drain electrode is electrically connected to the light-emitting element,

wherein the second transistor comprises a second oxide semiconductor layer,

wherein the third transistor comprises a third semiconductor layer,

wherein the first insulating layer comprises silicon oxide and a region in contact with the first oxide semiconductor layer,

wherein the second insulating layer comprises silicon oxide and a region in contact with the first oxide semiconductor layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises microcrystalline,

wherein in a channel length direction of the first oxide semiconductor layer, the first gate electrode is larger than the first oxide semiconductor layer, and the second gate electrode is smaller than the first oxide semiconductor layer, and

wherein a side surface of the first oxide semiconductor layer comprises a region which is not covered with the source electrode or the drain electrode.

13. The semiconductor device according to claim 12, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode.

14. The semiconductor device according to claim 13, wherein the pixel electrode comprises indium tin oxide.