Shielded trench devices

• US 10,714,574 B2
• Filed: 03/25/2019
• Issued: 07/14/2020
• Est. Priority Date: 05/08/2018
• Status: Active Grant

• Current Assignee: iPower Semiconductor, Co.
• Original Assignee: iPower Semiconductor, Co.
• Inventors: Yilmaz, Hamza
• Primary Examiner(s): Coleman, William
• Application Number:
  US16/363,812
• Publication Number:
  US 20190348510A1
• Time in Patent Office: 477 Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region that contacts a shield region in an epitaxial or crystalline layer of the device.

Claims

1. A trench device comprising:

a semiconductor layer of a first conductivity type;

a shield region of a second conductivity type in the semiconductor layer;

a shield polysilicon region of the second conductivity type on the shield region and confined laterally by first dielectric spacers;

a dielectric layer on the shield polysilicon region; and

a trench gate structure on the dielectric layer.

2. The device of claim 1, further comprising:

a body region of the second conductivity type adjacent to the trench gate structure; and

a source region of the first conductivity type inside the body region, the source region and the body region ohmically contacting a top electrode.

3. The device of claim 1, wherein the trench devices comprises a trench MOSFET or a trench IGBT.

4. The device of claim 1, further comprising a metal contact extending into a contact trench in the semiconductor layer, the contact trench being shallower in the semiconductor layer than is the gate structure.

5. The device of claim 1, wherein a charge carrier density in the shield region is substantially equal to a charge carrier density in the semiconductor layer.

6. The device of claim 1, further comprising:

a substrate of the first conductivity type, the semiconductor layer being on the substrate; and

a bottom electrode on a bottom surface of the substrate.

7. The device of claim 1, further comprising:

a substrate of the second conductivity type, the semiconductor layer being on the substrate; and

a bottom electrode on a bottom surface of the substrate.

8. The device of claim 1, wherein the first conductivity type is N type, and the second conductivity type is P type.

9. The device of claim 1, further comprising:

a second shield region of the second conductivity type in the semiconductor layer;

a second shield polysilicon region of the second conductivity type on the second shield region and confined laterally by dielectric spacers;

a second dielectric layer on the second shield polysilicon region; and

a second trench gate structure on the second dielectric layer.

10. The device of claim 1, wherein the semiconductor layer comprises a drift region of the trench device.

11. The device of claim 1, wherein the semiconductor layer is a crystalline silicon layer.

12. The device of claim 2, wherein the gate trench structure includes a gate having the first conductivity type and a gate dielectric between the gate and the body region.

13. A trench semiconductor device, comprising:

a substrate making ohmic contact to a bottom electrode;

a semiconductor layer of a first conductivity type, the semiconductor layer forming a junction with the substrate;

a plurality of shield regions of a second conductivity type in the semiconductor layer;

a plurality of shield polysilicon regions of the second conductivity type and confined laterally by dielectric spacers, the shield polysilicon regions respectively being on the shield regions; and

a plurality of gate trench structures respectively on the shield polysilicon regions, each of the gate trench structures including;

a dielectric layer on an underlying one of the shield polysilicon regions; and

a conductive gate on the dielectric layer.

14. The device of claim 13, further comprising:

a plurality of body regions of the second conductivity type adjacent to the gate trench structures;

a plurality of source regions of the first conductivity type in the body regions; and

a top electrode ohmically contacting the source regions and the body regions.

15. The trench semiconductor device of claim 13, wherein the first conductivity is N type, and the second conductivity is P type.

16. The device of claim 13, wherein the semiconductor layer comprises a drift region of the trench device.

17. The device of claim 13, wherein the semiconductor layer is a crystalline silicon layer.

18. The device of claim 14, further comprising an edge termination area including a plurality of rings, some of the rings including field plates enclosing an active device area.

19. The trench semiconductor device of claim 14, wherein:

the trench semiconductor device is an insulated gate bipolar transistor (IGBT);

the substrate has the second conductivity type;

the bottom electrode is a collector of the IGBT; and

the top electrode is an emitter of the IGBT.

20. The trench semiconductor device of claim 19, wherein one or more of the shield polysilicon regions in an active device area of the IGBT ohmically contact the emitter electrode and act to improve switching speed.

21. The trench semiconductor device of claim 19, wherein one or more of the shield polysilicon regions in an active device area of the IGBT floats and acts to minimize a voltage drop between the collector and the emitter of the IGBT.

22. A method of forming a vertical trench power device, the method comprising:

forming a plurality of gate trenches in a semiconductor layer of a first conductivity type, the semiconductor layer overlying a substrate;

forming dielectric spacers on sidewalls of the gate trenches;

forming shield regions of a second conductivity type in the semiconductor layer;

forming polysilicon shield regions of the second conductivity type in the gate trenches and in contact with the shield regions in the semiconductor layer, the polysilicon shield regions being confined laterally by the dielectric spacers on the sidewalls of the gate trenches;

forming dielectric spacers overlying the polysilicon shield regions; and

forming conductive gate structures in the gate trenches, the conductive gate structures overlying the dielectric spacers and the polysilicon shield regions.

23. The method of claim 22, wherein forming the shield regions in the semiconductor layer comprises implanting dopants of the second conductivity type into the semiconductor layer below bottoms of the gate trenches.

24. The method of claim 22, wherein forming the shield regions in the semiconductor layer comprises:

etching to extend the gate trenches below the dielectric spacers; and

selectively growing an epitaxial layer from a bottom of the gate trenches up to the dielectric spacers to form the shield regions of the second conductivity type in the semiconductor layer.

25. The method of claim 22, wherein forming the polysilicon shield regions comprises:

depositing a polysilicon layer into the gate trenches;

doping the polysilicon layer with dopants of the second conductivity type; and

etching down the polysilicon layer to leave the polysilicon shield regions at the bottoms of the gate trenches.

26. The method of claim 22, wherein forming the dielectric spacers comprises:

depositing a dielectric layer to completely fill the gate trenches;

planarizing the dielectric layer to form a planar top surface;

applying a mask to protect the dielectric layer in first areas of the gate trenches and to expose the dielectric layer in second areas of the gate trenches; and

etching down the dielectric layer through the mask to form the dielectric spacers in the second areas of the gate trenches and to leave the insulating layer filling the first areas of the gate trenches.

27. The method of claim 22, wherein forming the gate trenches comprises:

etching the semiconductor layer through a mask that exposes the semiconductor layer in areas of the gate trenches and in areas of body contact trenches, the etching forming the body contact trenches and forming an initial depth of the gate trenches, the gate trenches having a first width and the body contact trenches having a second width that differs from the first width, wherein;

depositing a dielectric layer in the body contact trenches and the initial depth of gate trenches, the dielectric layer being thick enough to completely fill the body contact trenches; and

isotropically etching the dielectric layer to remove the dielectric layer from the gate trenches while leaving dielectric material in the body contact trenches; and

selectively etching the semiconductor layer to deepen the gate trenches while the dielectric material in the body contact trenches prevents deepening of the body contact trenches.

28. The method of claim 22, wherein forming the gate trenches comprises:

etching the semiconductor layer through a first mask that exposes the semiconductor layer in areas of the gate trenches and in areas of body contact trenches, the etching forming the body contact trenches and forming an initial depth of the gate trenches, the gate trenches having a first width and the body contact trenches having a second width that differs from the first width, wherein;

depositing oxide into the body contact trenches and the gate trenches;

planarizing the oxide;

etching through a second mask that protects the areas of the body contact trenches and exposes the areas of the gate trenches, to remove the oxide from the gate trenches; and

further etching the semiconductor layer in the areas of the gate trenches to make the gate trenches deeper than the body contacts trenches.

29. The method of claim 22, wherein forming conductive gate structures comprises:

growing a gate oxide in the gate trenches and covering mesas of the semiconductor layer between the gate trenches;

depositing a polysilicon layer of the first conductivity to fill the gate trenches; and

planarizing the polysilicon layer with respect to a surface of the semiconductor layer.

30. The method of claim 22, wherein the first conductivity is N type, and the second conductivity is P type.

31. The method of claim 22, wherein the substrate is P type with an N type field stop layer, and the vertical trench power device comprises a power IGBT.

32. The method of claim 22, wherein forming the polysilicon shield regions comprises:

depositing a polysilicon layer of the second conductivity type into the gate trenches;

planarizing the polysilicon layer at a surface of the semiconductor layer;

applying a first mask to protect the polysilicon layer in first areas of the gate trenches and to expose the polysilicon layer in second areas of the gate trenches; and

etching the polysilicon layer through the first mask to leave the polysilicon layer extending to a surface of the semiconductor layer in the first areas of the gate trenches and to form the polysilicon shield regions that are confined laterally by the dielectric spacer in the second areas regions.

33. The method of claim 23, wherein implanting the dopants comprises ion implanting the dopants of the second conductivity using a plurality of energies and a plurality of doses to form the shield regions of the second conductivity type in the semiconductor layer.

34. The process of claim 29, further comprising:

implanting dopants of the second conductivity type though a first mask layers into the semiconductor layer to form body regions of the second conductivity type in the semiconductor layer;

implanting dopants of the first conductivity type though a second mask into the semiconductor layer to form source regions of the first conductivity type in the body regions;

depositing a BPSG overlying the semiconductor layer;

etching contact regions and saw street areas through a third mask;

sputtering a metal layer;

etching the metal layer through a fourth mask;

depositing a passivation layer;

etching the passivation layer through a fifth mask to remove the passivation layer from bonding pads and saw streets;

grinding a backside of the substrate; and

depositing a metal layer on the backside of the substrate.

35. The process of claim 32, further comprising:

implanting dopants of the second conductivity type though a second mask into the semiconductor layer to form body regions of the second conductivity type in the semiconductor layer;

implanting dopants of the first conductivity type though a third mask into the semiconductor layer to form source regions of the first conductivity type in the body regions;

depositing an insulating layer overlying the semiconductor layer; and

etching through a fourth mask to form an opening through the insulating layer to the polysilicon layer in the first areas of the gate trenches.