Gate-all-around field-effect-transistor devices and fabrication methods thereof

• US 10,714,585 B2
• Filed: 07/31/2018
• Issued: 07/14/2020
• Est. Priority Date: 08/08/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Zhou, Fei
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US16/050,900
• Publication Number:
  US 20190051729A1
• Time in Patent Office: 714 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for fabricating a gate-all-around field-effect-transistor device includes forming a plurality of first stacked structures, each including a first sacrificial layer and a first semiconductor layer; forming a first dummy gate structure across the first stacked structures and partially covering the top and the sidewall surfaces of each first stacked structure, and a first sidewall spacer on each sidewall surface of the first dummy gate structures; forming a first source/drain doped layer, and a dielectric structure exposing the top surfaces of the first dummy gate structure and each first sidewall spacer; removing the first dummy gate structure to form a first trench; removing a portion of the first sacrificial layer to form a first via which partially exposes the first source/drain doped layer; forming a first barrier layer on the first source/drain doped layer; and forming a first gate structure to fill the first trench and the first via.

Claims

1. A method for fabricating a gate-all-around (GAA) field-effect-transistor (FET) device, comprising:

providing a base substrate and forming a plurality of first stacked structures on the base substrate, wherein each first stacked structure includes a first sacrificial layer and a first semiconductor layer formed on the first sacrificial layer;

forming a first dummy gate structure across the plurality of first stacked structures, and a first sidewall spacer on each sidewall surface of the first dummy gate structure, wherein the first dummy gate structure is formed on a portion of the base substrate and covers a portion of a top surface and a portion of each sidewall surface of the plurality of first stacked structures;

forming a first source/drain doped layer in the plurality of first stacked structures on each side of the first dummy gate structure and separated from the first dummy gate structure by a first sidewall spacer;

forming a dielectric structure on the base substrate to cover the plurality of first stacked structures and the first source/drain doped layer, wherein the dielectric structure exposes a top surface of the first dummy gate structure and a top surface of each first sidewall spacer;

removing the first dummy gate structure to form a first trench in the dielectric structure;

removing a portion of the first sacrificial layer exposed in the first trench to form a first via under the first semiconductor layer, wherein sidewalls of the first via expose a portion of the sidewalls of the first source/drain doped layer;

forming a first barrier layer directly on a portion of the sidewalls of the first source/drain doped layer exposed by the first via; and

forming a first gate structure to fill the first trench and the first via.

2. The method according to claim 1, wherein:

the base substrate includes a substrate including a core region, a first fin structure formed in the core region, and an isolation structure covering sidewall surfaces of the first fin structure, wherein the plurality of first stacked structures are formed on the first fin structure.

3. The method according to claim 2, wherein forming the first source/drain doped layer includes:

forming a first source/drain trench in the plurality of first stacked structures on each side of the first dummy gate structure and separated from the first dummy gate structure by a first sidewall spacer; and

forming the first source/drain doped layer, containing doped ions, in the first source/drain trench.

4. The method according to claim 3, wherein:

forming the first source/drain doped layer in the first source/drain trench includes an epitaxial growth process; and

the doping ions are implanted into the first source/drain doped layer through an in-situ ion implantation process.

5. The method according to claim 4, wherein:

a process gas used in the epitaxial growth process includes H₂, HCl, Cl₂H₂Si, and PH₃;

a process temperature of the epitaxial growth process is in a range of approximately 650°

C. to 850°

C.; and

the doped ions include P-type ions.

6. The method according to claim 3, wherein, and:

a bottom of the first source/drain trench exposes the first sacrificial layer;

the first via also exposes a bottom portion of the first source/drain doped layer; and

the first barrier layer is also formed on the bottom of the first source/drain trench.

7. The method according to claim 3, prior to performing the self-aligned silicide process, further including:

a bottom of the first source/drain trench exposes the first fin structure; and

the first source/drain doped layer is formed on the first fin structure.

8. The method according to claim 3, wherein the substrate further includes a peripheral region, and a second fin structure formed in the peripheral region, the isolation structure also covering sidewall surfaces of the second fin structure, and the method further includes:

forming a plurality of second stacked structures on the second fin structure, wherein each second stacked structure includes a second sacrificial layer, and a second semiconductor layer formed on the second sacrificial layer,

forming a second dummy gate structure across the plurality of second stacked structures, and a second sidewall spacer on each sidewall surface of the second dummy gate structure, wherein the second dummy gate structure is formed on a portion of the base substrate and covers a portion of a top surface and a portion of each sidewall surface of the plurality of second stacked structures;

prior to forming the dielectric structure on the base substrate, forming a second source/drain doped layer in the plurality of second stacked structures on each side of the second dummy gate structure and separated from the second dummy gate structure by a second sidewall spacer, wherein after forming the dielectric structure, the dielectric structure also covers the plurality of second stacked structures and the second source/drain doped layer and exposes top surfaces of the second dummy gate structure and the second sidewall spacers;

removing the second dummy gate structure to form a second trench in the dielectric structure;

removing a portion of the second sacrificial layer exposed in the second trench to form a second via under the second semiconductor layer, sidewalls of the second via exposing a portion of the second source/drain doped layer;

forming a second barrier layer on a portion of the second source/drain doped layer exposed by the second via; and

forming a second gate structure to fill the second trench and the second via.

9. The method according to claim 8, wherein:

forming the second source/drain doped layer includes;

forming a second source/drain trench in the plurality of second stacked structures on each side of the second dummy gate structure and separated from the second dummy gate structure by a second sidewall spacer, wherein a bottom of the second source/drain trench exposes the second sacrificial layer, and

forming the second source/drain doped layer, containing doped ions, in the second source/drain trench;

the second via also exposes bottom portion of the second source/drain doped layer; and

the second barrier layer is also formed on the bottom of the second source/drain trench.

10. The method according to claim 8, wherein:

the second source/drain doped layer has a bottom formed in the second semiconductor layer and cuts through the second sacrificial layer.

11. The method according to claim 1, wherein:

the first sacrificial layer is made of a material including at least one of SiB, SiGe, SiC, SiP, SiAs, SiGeB, SiCB, GaN, InAs, and InP;

the first semiconductor layer is made of a material including at least one of SiB, SiGe, SiC, SiP, SiAs, SiGeB, SiCB, GaN, InAs, and InP, wherein;

the first semiconductor layer and the first sacrificial layer are made of different materials.

12. The method according to claim 1, wherein:

the first barrier layer is made of a material including one of SiO_x and SiON.

13. The method according to claim 12, wherein:

a thickness of the first barrier layer is in a range of approximately 8 Å

to 45 Å

.

14. The method according to claim 1, wherein:

the first via is formed by a wet etching process.

15. The method according to claim 14, wherein:

an etching solution used in the wet etching process includes HCl.

16. The method according to claim 1, wherein:

the first source/drain doped layer contains doping ions; and

a concentration of the doping ions in the first source/drain doped layer is in a range of approximately 5.0E20 atom/cm³ and 1.0E22 atom/cm³.

17. The method according to claim 1, prior to forming the first dummy gate structure, further including:

forming a dummy gate oxide layer on the base substrate to cover a portion of the top surface and a portion of each sidewall surface of the plurality of first stacked structures.

18. The method according to claim 17, after forming the first trench, further including:

removing a portion of the dummy gate oxide layer formed on the bottom of the first trench.

19. The method according to claim 1, wherein:

the first source/drain doped layer is formed directly on the base substrate and cuts through the first sacrificial layer and the first semiconductor layer, and

the sidewalls of the first source/drain doped layer are coplanar with sidewalls of the first sidewall spacer.