Method and structure for FinFET devices

• US 10,714,615 B2
• Filed: 12/17/2018
• Issued: 07/14/2020
• Est. Priority Date: 01/27/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Kuo-Yin, Tsai, Teng-Chun, Lin, Po-Yu
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Fox, Brandon C
• Application Number:
  US16/222,322
• Publication Number:
  US 20190140097A1
• Time in Patent Office: 575 Days
• Field of Search: 257347, 257401, 438703
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Claims

1. A method comprising:

providing a substrate that includes a first region doped with a first dopant of a first type and a second region doped with a second dopant of a second type that is different from the first type;

forming a first semiconductor layer on the second region such that at least part of the first region is free of the first semiconductor layer, wherein the first semiconductor layer includes a third dopant of the second type;

forming a second semiconductor layer on the first region such that at least part of the second region is free of the second semiconductor layer, wherein the second semiconductor layer includes a fourth dopant of the first type;

recessing the first region of the substrate prior to forming the second semiconductor layer on the first region of the substrate; and

patterning the first semiconductor layer to form a first fin structure and patterning the second semiconductor layer to form a second fin structure.

2. The method of claim 1, wherein patterning the first semiconductor layer to form the first fin structure further includes patterning second region of the substrate to from the first fin structure, and

wherein patterning the second semiconductor layer to form the second fin structure further includes patterning first region of the substrate to from the second fin structure.

3. The method of claim 1, wherein the first fin structure is free of the second semiconductor layer.

4. The method of claim 1, wherein the second fin structure is free of the first semiconductor layer.

5. The method of claim 1, further comprising recessing the second region of the substrate prior to forming the first semiconductor layer on the second region of the substrate.

6. The method of claim 1, wherein after the forming of the first semiconductor layer on the second region, the first semiconductor layer is positioned at a first height above the substrate, and

wherein after the forming of the second semiconductor layer on the first region, the second semiconductor layer is positioned at a second height above the substrate that is greater than the first height.

7. The method of claim 1, further comprising performing a planarization process on the first semiconductor layer on the second region and the second semiconductor layer on the first.

8. A method comprising:

providing a substrate that includes a first region doped with a first dopant of a first type and a second region doped with a second dopant of a second type that is opposite from the first type;

forming a first semiconductor layer on the second region, wherein the first semiconductor layer includes a third dopant of the second type;

forming a second semiconductor layer on the first region such that the second semiconductor layer interfaces with the first semiconductor layer formed on the second region, wherein the second semiconductor layer includes a fourth dopant of the first type; and

patterning the first semiconductor layer to form a first fin structure and patterning the second semiconductor layer to form a second fin structure.

9. The method of claim 8, further comprising removing a portion of the second region of the substrate prior to forming the first semiconductor layer on the second region of the substrate.

10. The method of claim 8, further comprising removing a portion of the first region of the substrate prior to forming the second semiconductor layer on the first region of the substrate.

11. The method of claim 8, wherein forming the first semiconductor layer on the second region of the substrate includes forming the first semiconductor layer directly on the second region of the substrate such that the first semiconductor layer physically contacts the second region of the substrate, and

wherein forming the second semiconductor layer on the first region of the substrate includes forming the second semiconductor layer directly on the first region of the substrate such that the second semiconductor layer physically contacts the first region of the substrate.

12. The method of claim 8, further comprising planarizing the first semiconductor layer and the second semiconductor layer prior to patterning the first semiconductor layer to form the first fin structure and patterning the second semiconductor layer to form the second fin structure.

13. The method of claim 8, wherein patterning the first semiconductor layer to form the first fin structure includes patterning the second region of the substrate to form the first fin structure,

wherein patterning the second semiconductor layer to form the second fin structure includes patterning the first region of the substrate to form the second fin structure,

wherein the first fin structure is free of the second semiconductor layer, and

wherein the second fin structure is free of the second semiconductor layer.

14. The method of claim 8, further comprising forming an isolation structure between the first fin structure and the second fin structure.

15. A method comprising:

providing a substrate, wherein the substrate has a first region and a second region that is adjacent to the first region, the first and second regions are doped with first and second dopants respectively, and the first and second dopants are of opposite types;

recessing the second region of the substrate to form a recessed second region of the substrate;

forming a first semiconductor layer on the recessed second region, wherein the first semiconductor layer is doped with a third dopant and the first and third dopants are of opposite types;

recessing the first region of the substrate to form a recessed first region of the substrate; and

forming a second semiconductor layer on the recessed first region, wherein the second semiconductor layer is doped with a fourth dopant and the first and fourth dopants are of a same type.

16. The method of claim 15, wherein the first semiconductor layer is formed of a different semiconductor material than the second semiconductor layer.

17. The method of claim 15, further comprising patterning the first semiconductor layer and the recessed second region of the substrate to form a first fin structure and patterning the second semiconductor layer and the recessed first region of the substrate to form a second fin structure.

18. The method of claim 15, wherein after forming the second semiconductor layer on the recessed first region, a portion of the second semiconductor layer physically contacts the first semiconductor layer.

19. The method of claim 15, wherein the first semiconductor layer physically contacts the recessed second region of the substrate, and

wherein the second semiconductor layer physically contacts the recessed first region of the substrate.

20. The method of claim 15, wherein the second semiconductor layer is disposed at a greater height above the substrate than the first semiconductor layer after forming the second semiconductor layer on the recessed first region.