Power control by direct drive

• US 10,715,116 B2
• Filed: 03/29/2017
• Issued: 07/14/2020
• Est. Priority Date: 04/01/2016
• Status: Active Grant

• Current Assignee: King Kuen Hau
• Original Assignee: King Kuen Hau
• Inventors: Hau, King Kuen
• Primary Examiner(s): Tra, Anh Q
• Application Number:
  US16/081,932
• Publication Number:
  US 20190089336A1
• Time in Patent Office: 1,203 Days
• Field of Search: 327333
• CPC Class Codes: G06G 7/163 using a variable impedance controlled by one of the input signals, variable amplification or transfer function G06G7/161, G06G7/162 take precedence
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/0048 Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/342 Active non-dissipative snubbers
• CPC Class Codes: H02M 3/06 using resistors or capacitors, e.g. potential divider
• CPC Class Codes: H02M 7/06 using discharge tubes without control electrode or semiconductor devices without control electrode
• CPC Class Codes: H03H 5/12 with at least one voltage- or current-dependent element
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power control circuit comprising a power supply and a load, the load being synthesized from an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped in impedance modules. The impedance elements in each impedance module are of equal value, while those between the modules bear ratios uniquely defined according to the numbers of impedance elements in the impedance modules. A number of switches associated with said impedance elements short out a selected number of the impedance elements under the control of a first analog signal which may be preprocessed by an analytic function. The analog signal is converted to digital signals by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, whereby the amount of power delivered to the load is controllable by the first analog signal. Pulse-width-modulation is deployed to further control the power by a second analog signal, with additional benefit of overload protection.

Claims

1. A level shifting circuit between a first voltage level and a second voltage level, the second voltage level being higher than the first voltage level, comprising:

a first current source coupled between the first voltage level and the second voltage level, wherein the first current source is driven on and off by a first signal, said first signal alternating between two signal levels; and

a current-to-voltage converter to convert the current from the first current source to an output signal at the second voltage level;

a noise suppression means configured to mitigate noise pulses on the converter, the pulses being induced by voltage excursion of the second voltage level with respect to the first voltage level;

whereby the first signal is level shifted to the second voltage level as the output signal.

2. A level shifting circuit of claim 1, wherein the noise suppression means is comprising:

a positive pulse detector monitoring the second voltage level with respect to the first voltage level, detection being enabled by a second signal, the second signal being anti-phase to the first signal;

a negative pulse detector monitoring the second voltage level with respect to the first voltage level, detection being enabled by the first signal;

a first bleeder coupled in parallel to the converter, the first bleeder being turned on when a positive pulse is detected;

a second bleeder coupled in parallel to the first current source, the second bleeder being turned on when a negative pulse is detected.

3. The level shifting circuit of claim 1, wherein the current-to-voltage converter is a resistor or a Zener diode.

4. A level shifting circuit of claim 1, wherein the noise suppression means is comprising:

a second current source driven by a second signal, the second signal being anti-phase to the first signal;

a third current source driven by the first signal;

wherein;

a first bleeder is enabled by the second signal through the second current source; and

a switch is turned on by the third current source to disable the first bleeder.

5. A level shifting circuit of claim 1, wherein the current-to-voltage converter is a capacitor;

and wherein the noise suppression means is comprising;

a second current source coupled between the first voltage level and the second voltage level, wherein the second current source is driven on and off by a second signal, the second signal being anti-phase to the first signal;

a first bleeder is coupled parallel to the converter and is enabled by the second current source;

a voltage limiting device coupled between the first current source and the second voltage level;

a rectifying charger coupled between the first current source and the capacitor, wherein the charger is driven to charge the capcitor by a voltage limited by the voltage limiting device.

6. The level shifting circuit of claim 5, wherein:

the voltage limiting device is a Zener diode; and

the first bleeder is a controllable switch.

7. The level shifting circuit of claim 5, wherein the rectifying charger is comprising a voltage buffer coupled in cascade with a rectifying diode.

13. A power control circuit, comprising:

a power supply;

a load coupled to the power supply, the load being a two-terminal network comprising a plurality of impedance elements connected in series, wherein the impedance elements are configured to be switched in or out of the network by a plurality of switches;

an analog-to-digital converter with an input line receiving an analog signal, and a plurality of digital output lines coupled to control the switches through a plurality of level shifters of claim 1;

whereby the power delivered to the load is controlled as the impedance of the load is controlled by the analog signal.

14. The power control circuit of claim 13, further comprising a function generator coupled to preprocess the analog signal with a predetermined function.

15. The power control circuit of claim 13, wherein the analog signal is representative of a voltage, a current or a power of the load.

16. The power control circuit of claim 13, further comprising:

a power switch coupled between the power supply and the load;

a pulse-width-modulation driver, wherein the power switch is driven by a modulation signal generated by the driver at a duty cycle according to the modulation signal.

17. The power control circuit of claim 16, wherein the pulse-width-modulation driver is comprising:

an input line coupled to receive a driver input signal;

an output line coupled to deliver a driver output signal;

an averaging circuit to determine a time average of the driver input signal;

a first comparator to compare the driver input signal to a predetermined first threshold, wherein the first comparator outputs a triggering signal when the driver input signal goes higher than the first threshold;

a pulse extender coupled to be triggered by the triggering signal to generate a pulse of a predetermined width;

an analog-OR circuit with a first input coupled to receive the time average of the driver input signal, and a second input coupled to receive the output from the pulse extender;

a second comparator to compare the output of the analog-OR circuit with a predetermined second threshold;

wherein the output of the second comparator is coupled to the output line;

whereby the driver output signal is low when the output of the analog-OR circuit is higher than the second threshold.

8. A method of level shifting between a first voltage level and a second voltage level, the second voltage level being higher than the first voltage level, comprising the steps of:

coupling a first current source between the first voltage level and the second voltage level;

driving the first current source on and off by a first signal, wherein the first signal is alternating between two signal levels;

converting the current from the first current source to an output signal at the second voltage level by a current-to-voltage converter; and

mitigating noise pulses on the converter, the pulses being induced by voltage excursion of the second voltage level with respect to the first voltage level;

whereby the first signal is level shifted to an output signal at the second voltage level.

9. The method of level shifting of claim 8, wherein the current-to-voltage converter is a resistor or a Zener diode, and wherein the step of mitigating noise pulses is comprising the steps of:

coupling a first bleeder in parallel to the converter;

coupling a second bleeder in parallel to the first current source;

monitoring the second voltage level with respect to the first voltage level by a positive pulse detector, the detector being enabled by a second signal, the second signal being anti-phase to the first signal;

monitoring the second voltage level with respect to the first voltage level by a negative pulse detector, the detector being enabled by the first signal;

turning on the first bleeder when a positive pulse is detected;

turning on the second bleeder when a negative pulse is detected.

10. The method of level shifting of claim 8, wherein the step of mitigating noise pulses is comprising the steps of:

coupling a first bleeder in parallel to the converter;

driving a second current source by a second signal, the second signal being anti-phase to the first signal;

enabling the first bleeder by the second signal through the second current source;

driving a third current source by the first signal;

turning on a switch by the third current source to disable the first bleeder.

11. The method of level shifting of claim 8, wherein

the current-to-voltage converter is a capacitor, wherein the step of mitigating noise pulses is comprising the steps of:

coupling a first bleeder in parallel to the converter;

enabling the first bleeder by a second current source, said second current source being driven by the second signal;

coupling a voltage limiting device between the first current source and the second voltage level;

coupling a rectifying charger between the first current source and the capacitor, and through the rectifying charger charging the capcitor by a voltage limited by the voltage limiting device.

12. The method of level shifting of claim 11, wherein the voltage limiting device is a Zener diode.

18. A method of power control, comprising the steps of:

coupling a load to a power supply;

controlling the load impedance through impedance synthesis by the steps of;

coupling in series a plurality of impedance elements to form a two-terminal network;

converting an analog signal to a plurality of digital signals by an analog-to-digital converter;

coupling the digital signals to control the switches by the method of level shifting of claim 8;

switching the impedance elements in or out of the network by a plurality of switches driven by the plurality of digital signals;

whereby the power delivered to the load is controlled as the impedance of the load is controlled by the analog signal.

19. The method of claim 18, further comprising a step of preprocessing the analog signal with a predetermined function.

20. The method of claim 18, wherein the analog signal is representative of a voltage, a current or a power of the load.

21. The method of claim 18, further comprising a step of pulse-width-modulating the on-time of a power switch coupled between the power supply and the load, whereby the load current is modulated at a duty cycle according to a digital modulation signal.

22. The method of claim 21, wherein the digital modulation signal is generated by the steps of:

determining a time average of the second analog signal by an averaging circuit;

comparing the second analog signal with a first threshold by a first comparator, and generating a trigger pulse when the second analog signal goes higher than a first predetermined threshold;

triggering a pulse extender for an extended pulse of predetermined time period;

performing an analog-OR function on the time average of the second analog signal and the extended pulse by an analog-OR gate;

comparing an output of the analog-OR gate with a second threshold by a second comparator;

whereby the output of the second comparator is the digital modulation signal.