Comparator hysteresis circuit

• US 10,715,117 B1
• Filed: 08/20/2019
• Issued: 07/14/2020
• Est. Priority Date: 08/20/2019
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sakurai, Satoshi
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US16/544,990
• Time in Patent Office: 329 Days
• Field of Search: None
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a timing circuit. The first transistor and the second transistor are coupled as a differential pair and are configured to compare an input signal to a hysteresis voltage. The first switch is coupled to the first transistor and is configured to selectably enable the first transistor. The second switch is coupled to the second transistor and is configured to selectably enable the second transistor. The timing circuit is coupled to the first switch and the second switch and is configured to close the first switch responsive to a signal transition at an output of the comparator circuit and close the second switch a predetermined delay time after the first switch is closed.

Claims

1. A comparator circuit, comprising:

a signal input terminal;

an output terminal;

a first transistor comprising a first terminal coupled to a first hysteresis voltage circuit;

a second transistor, comprising;

a first terminal coupled to the signal input terminal; and

a second terminal coupled to a second terminal of the first transistor;

a third transistor, comprising;

a first terminal coupled to a third terminal of the first transistor; and

a second terminal coupled to a power rail;

a fourth transistor, comprising;

a first terminal coupled to a third terminal of the second transistor; and

a second terminal coupled to the power rail; and

a timing circuit, comprising;

an input terminal coupled to the output terminal;

a first output coupled to a third terminal of the third transistor;

a second output coupled to a third terminal of the fourth transistor; and

a delay circuit, comprising;

an input terminal coupled to the first output; and

an output terminal coupled to the second output;

further comprising;

a fifth transistor, comprising;

a first terminal coupled to the second terminal of the fourth transistor; and

a second terminal coupled to a third output of the timing circuit.

2. The comparator circuit of claim 1, wherein the third output of the timing circuit is coupled to the input terminal of the timing circuit.

3. The comparator circuit of claim 1, further comprising:

a sixth transistor comprising;

a first terminal coupled to the signal input terminal;

a second terminal coupled to the second terminal of the first transistor; and

a third terminal coupled to a third terminal of the fifth transistor.

4. The comparator circuit of claim 1, further comprising:

a sixth transistor, comprising;

a first terminal coupled to the second terminal of the third transistor; and

a second terminal coupled to a fourth output of the timing circuit.

5. The comparator circuit of claim 4, further comprising:

a seventh transistor comprising;

a first terminal coupled to a second hysteresis voltage circuit; and

a second terminal coupled to the second terminal of the first transistor; and

a third terminal coupled to a third terminal of the sixth transistor.

6. The comparator circuit of claim 4, wherein:

the delay circuit is a first delay circuit; and

the timing circuit comprises a second delay circuit comprising;

an input terminal coupled to the third output; and

an output terminal coupled to the fourth output.

7. A comparator circuit, comprising:

a first transistor and a second transistor coupled as a differential pair, and configured to compare an input signal to a hysteresis voltage;

a first switch coupled to the first transistor, and configured to selectably enable the first transistor;

a second switch coupled to the second transistor, and configured to selectably enable the second transistor;

a timing circuit coupled to the first switch and the second switch, and configured to;

close the first switch responsive to a signal transition at an output terminal of the comparator circuit; and

close the second switch a predetermined delay time after the first switch is closed.

8. The comparator circuit of claim 7, wherein:

the signal transition is a first signal transition; and

the timing circuit is configured to open the first switch and the second switch responsive to a second signal transition at the output terminal of the comparator circuit.

9. The comparator circuit of claim 8, wherein the timing circuit is configured to open the first switch and the second switch with no predetermined delay between opening of the first switch and opening of the second switch.

10. The comparator circuit of claim 7, wherein:

the hysteresis voltage is a first hysteresis voltage;

the comparator circuit further comprises;

a third transistor and a fourth transistor coupled as a differential pair, and configured to compare the input signal to a second hysteresis voltage;

a third switch coupled to the third transistor, and configured to selectably enable the third transistor;

a fourth switch coupled to the fourth transistor, and configured to selectably enable the fourth transistor; and

the timing circuit is coupled to the third switch and the fourth switch and is configured to open the third switch and the fourth switch responsive to the signal transition at the output terminal of the comparator circuit.

11. The comparator circuit of claim 10, wherein the timing circuit is configured to open the third switch and the fourth switch with no predetermined delay between opening of the third switch and opening of the fourth switch.

12. The comparator circuit of claim 10, wherein:

the signal transition is a first signal transition; and

the timing circuit is configured to;

close the third switch responsive to a second signal transition at the output terminal of the comparator circuit; and

close the fourth switch the predetermined delay time after the third switch is closed.

13. The comparator circuit of claim 7, further comprising output circuitry coupled to the first switch and the second switch;

wherein the predetermined delay time is at least a long as a difference of propagation delay from the first switch through the output circuitry and propagation delay from the second switch through the output circuitry.

14. A comparator circuit, comprising:

a signal input terminal;

an output terminal;

a first input circuit, comprising;

a first transistor comprising a first terminal coupled to a first hysteresis voltage circuit;

a second transistor, comprising;

a first terminal coupled to the signal input terminal; and

a second terminal coupled to a second terminal of the first transistor;

a third transistor, comprising;

a first terminal coupled to a third terminal of the first transistor; and

a second terminal coupled to a power rail; and

a fourth transistor, comprising;

a first terminal coupled to a third terminal of the second transistor; and

a second terminal coupled to the power rail;

a second input circuit, comprising;

a fifth transistor comprising a first terminal coupled to a second hysteresis voltage circuit;

a sixth transistor, comprising;

a first terminal coupled to the signal input terminal; and

a second terminal coupled to a second terminal of the fifth transistor;

a seventh transistor, comprising;

a first terminal coupled to a third terminal of the fifth transistor; and

a second terminal coupled to the power rail; and

an eighth transistor, comprising;

a first terminal coupled to a third terminal of the sixth transistor; and

a second terminal coupled to the power rail; and

a timing circuit, comprising;

an input terminal coupled to the output terminal;

a first output coupled to a third terminal of the third transistor;

a second output coupled to a third terminal of the fourth transistor;

a third output coupled to a third terminal of the seventh transistor; and

a fourth output coupled to a third terminal of the eighth transistor.

15. The comparator circuit of claim 14, wherein the timing circuit comprises a delay circuit comprising:

an input terminal coupled to the first output; and

an output terminal coupled to the second output.

16. The comparator circuit of claim 15, further comprising output circuitry coupled to the third transistor and the fourth transistor, wherein the delay circuit is configured to provide between the first output and the second output a delay that is at least a long as a difference of propagation delay from the third transistor through the output circuitry and propagation delay from the fourth transistor through the output circuitry.

17. The comparator circuit of claim 14, wherein the timing circuit comprises a delay circuit, comprising:

an input terminal coupled to the fourth output; and

an output terminal coupled to the third output.

18. The comparator circuit of claim 14, wherein the timing circuit is configured to:

responsive to a signal transition at the output terminal;

turn off the seventh transistor and the eighth transistor;

turn on the third transistor; and

turn on the fourth transistor a predetermined delay time after the third transistor is turned on.

19. The comparator circuit of claim 18, wherein:

the signal transition is a first signal transition; and

the timing circuit is configured to;

responsive to a second signal transition at the output terminal;

turn off the third transistor and the fourth transistor;

turn on the seventh transistor responsive to the signal transition; and

turn on the eighth transistor a predetermined delay time after the seventh transistor is turned on.