Management device, information processing device, and management method

• US 10,719,436 B2
• Filed: 08/29/2017
• Issued: 07/21/2020
• Est. Priority Date: 03/03/2017
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshimura, Shiyo, Kanai, Tatsunori, Shirota, Yusuke, Shirai, Satoshi
• Primary Examiner(s): Grullon, Francisco A
• Application Number:
  US15/689,009
• Publication Number:
  US 20180253374A1
• Time in Patent Office: 1,057 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 16/22 Indexing; Data structures therefor; Storage structures
• CPC Class Codes: G06F 16/23 Updating
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0602 specifically adapted to achieve a particular effect
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

According to an embodiment, a management device includes a counter storage unit, a first management information storage unit, and an update unit. The first management information storage unit stores a first management table capable of storing first management information about each of a predetermined number of first areas. The first management information indicates whether each second area included in a corresponding first area has data written therein. In response to writing of first data into the nonvolatile memory, when a state of a target second area indicated in the first management information about a target first area is an unwritten state, the update unit changes the state of the target second area to a written state; while when the state of the target second area indicated in the first management information is the written state, the update unit updates the counter value for the target first area.

Claims

1. A management device that manages a nonvolatile memory,

the nonvolatile memory including a plurality of first areas,

each of the plurality of first areas including a plurality of second areas,

each of the plurality of second areas being a unit of rewriting data to the nonvolatile memory by a processing circuit,

the management device comprising:

a memory; and

a hardware processor, wherein

the memory is configured to store therein a counter value for each of the plurality of first areas, and

the memory is configured to store therein a first management table capable of storing first management information about each of a predetermined number of first areas; and

the hardware processor is configured to update the counter value and the first management table and perform wear leveling control on the nonvolatile memory on the basis of the counter value for each of the plurality of first areas, wherein

the first management information indicates whether each of a plurality of second areas included in a corresponding first area has data written therein, and

in response to writing of first data into the nonvolatile memory, the hardware processor is configured to;

when a state of a target second area indicated in the first management information about a target first area is an unwritten state, change the state of the target second area to a written state, the target first area being the first area into which the first data is to be written, the target second area being the second area into which the first data is to be written, and

when the state of the target second area indicated in the first management information is the written state, set all of the second areas other than the target second area indicated in the management information to the unwritten state, and update the counter value for the target first area.

2. The device according to claim 1, wherein

the first management table is capable of storing the first management information about first areas smaller in number than the number of the plurality of first areas included in the nonvolatile memory.

3. The device according to claim 1, wherein

when there is no first management information about the target first area in the first management table, the hardware processor is configured to perform a management information generation process, and

in the management information generation process, the hardware processor is configured to:

when there is an unused entry in the first management table, write the first management information about the target first area to the unused entry,

when there is no unused entry in the first management table, erase the first management information having been written into any of in-use entries to write the first management information about the target first area, and

update the counter value of a first area having been managed by the erased first management information.

4. The device according to claim 3, wherein

when there is no unused entry in the first management table, the hardware processor is configured to erase an oldest first management information.

5. The device according to claim 1, wherein

each of the plurality of first areas is a data unit managed by the processing circuit.

6. The device according to claim 5, wherein

the processing circuit includes a cache memory configured to temporarily store therein data read from the nonvolatile memory, and

each of the plurality of second areas has a size equal to that of a cache line of the cache memory.

7. The device according to claim 1, wherein

in the nonvolatile memory, batch writing of data in units of first areas or writing of data in units of second areas is performed, and

when the batch writing of data in units of first areas is performed, the hardware processor is configured to update the counter value of a first area to which data is written.

8. The device according to claim 1, wherein

the first management table stores therein the first management information about a first area managed by a virtual storage mechanism that stores correspondence relation information indicating a correspondence between a logical address and a physical address, and

when the correspondence relation information is removed by the virtual storage mechanism, the hardware processor is configured to erase the corresponding first management information stored in the first management table and update the counter value for the first area having been managed by the erased first management information.

9. The device according to claim 1, wherein

each of the plurality of second areas includes a plurality of third areas,

the memory is configured to further store therein a second management table capable of storing therein second management information about each of a predetermined number of second areas,

the second management information indicates whether each of a plurality of third areas included in a corresponding second area has data written therein, and

in response to writing of the first data to the nonvolatile memory, the hardware processor is configured to perform a state updating process in such a manner to:

when a state of a target third area indicated in the second management information about the target second area is a unwritten state, change the state of the target third area to a written state, the target third area being the third area into which the first data is to be written, and

when the state of the target third area indicated in the second management information is the written state, update the state of the target second area indicated in the first management information about the first area including the target second area.

10. The device according to claim 9, wherein

when there is no second management information about the target second area in the second management table, the hardware processor is configured to perform a second management information generation process, and

in the second management information generation process,

the hardware processor is configured to:

perform a state updating process in such a manner to

when there is an unused entry in the second management table, write the second management information about the target second area to the unused entry,

when there is no unused entry in the second management table, erase the second management information having been written into any of in-use entries to write the second management information about the target second area, and

update a state of a second area from which data is to be erased indicated in the first management information about a first area including the second area from which data is to be erased, the erased second area being the second area having been managed by the second management information to be erased.

11. The device according to claim 10, wherein

in the state updating process, the hardware processor is configured to:

when the state of the target second area or the state of the second area from which data is to be erased, being indicated in the first management information about a first area to be updated including the target second area or the second area from which data, is an unwritten state, change the state of the target second area or the second area from which data is to be erased to a written state, and

when the state of the target second area or the second area from which data is to be erased, being indicated in the first management information about the first area to be updated, is the written state, update the counter value for the first area to be updated.

12. The device according to claim 11, wherein

when there is no first management information about the first area to be updated in the first management table, the hardware processor is configured to perform a first management information generation process, and

in the first management information generation process, the hardware processor is configured to:

when there is an unused entry in the second management table, write the first management information about the first area to be updated into an unused entry,

when there is no unused entry in the second management table, erase the second management information having been written into any of in-use entries to write the first management information about the target first area to be updated, and

update the counter value for a first area having been managed by the first management information to be erased.

15. The device according to claim 1, wherein in the wear leveling control,

the hardware processor controls a position into which data is written on the basis of the counter value for each of the plurality of first areas in such a manner that data are evenly written to a whole area in the nonvolatile memory.

13. An information processing device comprising:

a processing circuit;

a nonvolatile memory; and

a management device configured to manage the nonvolatile memory,

the nonvolatile memory including a plurality of first areas,

each of the plurality of first areas including a plurality of second areas,

each of the plurality of second areas being a unit of rewriting data to the nonvolatile memory by a processing circuit,

the management device including;

a memory; and

a hardware processor, wherein

the memory is configured to store therein a counter value for each of the plurality of first areas, and

the memory is configured to store therein a first management table capable of storing first management information about each of a predetermined number of first areas; and

the hardware processor is configured to update the counter value and the first management table and perform wear leveling control on the nonvolatile memory on the basis of the counter value for each of the plurality of first areas, wherein

the first management information indicates whether each of a plurality of second areas included in a corresponding first area has data written therein, and

in response to writing of first data into the nonvolatile memory, the hardware processor is configured to;

when a state of a target second area indicated in the first management information about a target first area is an unwritten state, change the state of the target second area to a written state, the target first area being the first area into which the first data is to be written, the target second area being the second area into which the first data is to be written, and

when the state of the target second area indicated in the first management information is the written state, set all of the second areas other than the target second area indicated in the management information to the unwritten state, and update the counter value for the target first area.

14. A management method performed in a management device that manages a nonvolatile memory,

the nonvolatile memory including a plurality of first areas,

each of the plurality of first areas including a plurality of second areas,

each of the plurality of second areas being a unit of rewriting data to the nonvolatile memory by a processing circuit,

the management device including:

a memory, wherein

the memory is configured to store therein a counter value for each of the plurality of first areas, and

the memory is configured to store therein a first management table capable of storing first management information about each of a predetermined number of first areas,

the first management information indicating whether each of a plurality of second areas included in a corresponding first area has data written therein,

the method comprising;

updating the counter value and the first management table and performing wear leveling control on the nonvolatile memory on the basis of the counter value for each of the plurality of first areas,

according to writing of first data to the nonvolatile memory,

changing, when a state of a target second area indicated in the first management information about a target first area is an unwritten state, the state of the target second area to a written state, the target first area being the first area into which the first data is to be written, the target second area being the second area into which the first data is to be written, and

when the state of the target second area indicated in the first management information is the written state, setting all of the second areas other than the target second area indicated in the management information to the unwritten state, and updating the counter value for the target first area.