Semiconductor memory device and data writing method

• US 10,720,194 B2
• Filed: 06/25/2019
• Issued: 07/21/2020
• Est. Priority Date: 06/29/2018
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Yamagami, Yoshinobu
• Primary Examiner(s): Le, Toan K
• Application Number:
  US16/452,365
• Publication Number:
  US 20200005838A1
• Time in Patent Office: 392 Days
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In a semiconductor memory device, a memory cell array includes a plurality of memory cells. A write circuit includes a negative potential generating circuit that generates a potential lower than a lower power supply potential applied to the memory cells. When a write mask signal indicates an enabled state, the write circuit activates the negative potential generating circuit, and supplies the potential generated by the negative potential generating circuit to a bit line to be supplied with low data. On the other hand, when the write mask signal indicates a disabled state, the write circuit supplies no data to bit line pairs, and inactivates the negative potential generating circuit.

Claims

1. A semiconductor memory device comprising:

a plurality of bit line pairs;

a plurality of word lines;

a memory cell array including a plurality of memory cells arranged in an array, each of the plurality of memory cells being provided between a first power supply with a first potential and a second power supply with a second potential lower than the first potential, and being connected to one of the bit line pairs and one of the word lines; and

a write circuit provided for one or more of the bit line pairs, and supplying data to the one or more of the bit line pairs in accordance with a bit value corresponding to the one or more of the bit line pairs of input data having a plurality of bits in a write operation, wherein

the write circuit

includes a negative potential generating circuit that generates a third potential lower than the second potential, and

receives a write mask signal with a plurality of bits each corresponding to respective one of the bit line pairs, the write mask signal indicating an enabled state in which data is to be supplied to the one of the bit line pairs or a disabled state in which no data is to be supplied to the one of the bit line pairs,

when the write mask signal indicates the enabled state, the write circuit supplies data to the one of the bit line pairs in accordance with a write clock and activates the negative potential generating circuit so as to supply the third potential generated by the negative potential generating circuit to one of bit lines included in the one of the bit line pairs, the one of the bit lines being supplied with low data, and

when the write mask signal indicates the disabled state, the write circuit supplies no data to the one of the bit line pairs and inactivates the negative potential generating circuit.

2. The semiconductor memory device according to claim 1, wherein

each of the bit line pairs includes a first bit line and a second bit line, and

the semiconductor memory device further comprises:

a first transistor having a drain connected to the first bit line, a source connected to an output node of the negative potential generating circuit, and a gate receiving data supplied from the write circuit to the first bit line; and

a second transistor having a drain connected to the second bit line, a source connected to the output node of the negative potential generating circuit, and a gate receiving data supplied from the write circuit to the second bit line.

3. The semiconductor memory device according to claim 1, wherein

each of the bit line pairs includes a first bit line and a second bit line, and

the semiconductor memory device further comprises:

a first buffer having an input receiving data supplied from the write circuit to the first bit line, an output connected to the first bit line, and a ground node connected to an output node of the negative potential generating circuit; and

a second buffer having an input receiving data supplied from the write circuit to the second bit line, an output connected to the second bit line, and a ground node connected to the output node of the negative potential generating circuit.

4. The semiconductor memory device according to claim 1, wherein

the write mask signal indicates the enabled state at one of a high level and a low level, and the disabled state at the other of the high level and the low level.

5. A method of writing data in a semiconductor memory device including:

a plurality of bit line pairs;

a plurality of word lines;

a memory cell array including a plurality of memory cells arranged in an array, each of the plurality of memory cells being provided between a first power supply with a first potential and a second power supply with a second potential lower than the first potential, and being connected to one of the bit line pairs and one of the word lines; and

a negative potential generating circuit that generates a third potential lower than the second potential,

the method comprising;

when data is to be supplied to one or more of the bit line pairs, activating the negative potential generating circuit in accordance with a write clock so as to supply the third potential generated by the negative potential generating circuit to one of bit lines included in the one or more of the bit line pairs, the one of the bit lines being supplied with low data; and

when no data is to be supplied to the one or more of the bit line pairs, inactivating the negative potential generating circuit.