Semiconductor memory device and data writing method
First Claim
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1. A semiconductor memory device comprising:
- a plurality of bit line pairs;
a plurality of word lines;
a memory cell array including a plurality of memory cells arranged in an array, each of the plurality of memory cells being provided between a first power supply with a first potential and a second power supply with a second potential lower than the first potential, and being connected to one of the bit line pairs and one of the word lines; and
a write circuit provided for one or more of the bit line pairs, and supplying data to the one or more of the bit line pairs in accordance with a bit value corresponding to the one or more of the bit line pairs of input data having a plurality of bits in a write operation, whereinthe write circuitincludes a negative potential generating circuit that generates a third potential lower than the second potential, andreceives a write mask signal with a plurality of bits each corresponding to respective one of the bit line pairs, the write mask signal indicating an enabled state in which data is to be supplied to the one of the bit line pairs or a disabled state in which no data is to be supplied to the one of the bit line pairs,when the write mask signal indicates the enabled state, the write circuit supplies data to the one of the bit line pairs in accordance with a write clock and activates the negative potential generating circuit so as to supply the third potential generated by the negative potential generating circuit to one of bit lines included in the one of the bit line pairs, the one of the bit lines being supplied with low data, andwhen the write mask signal indicates the disabled state, the write circuit supplies no data to the one of the bit line pairs and inactivates the negative potential generating circuit.
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Abstract
In a semiconductor memory device, a memory cell array includes a plurality of memory cells. A write circuit includes a negative potential generating circuit that generates a potential lower than a lower power supply potential applied to the memory cells. When a write mask signal indicates an enabled state, the write circuit activates the negative potential generating circuit, and supplies the potential generated by the negative potential generating circuit to a bit line to be supplied with low data. On the other hand, when the write mask signal indicates a disabled state, the write circuit supplies no data to bit line pairs, and inactivates the negative potential generating circuit.
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Citations
5 Claims
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1. A semiconductor memory device comprising:
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a plurality of bit line pairs; a plurality of word lines; a memory cell array including a plurality of memory cells arranged in an array, each of the plurality of memory cells being provided between a first power supply with a first potential and a second power supply with a second potential lower than the first potential, and being connected to one of the bit line pairs and one of the word lines; and a write circuit provided for one or more of the bit line pairs, and supplying data to the one or more of the bit line pairs in accordance with a bit value corresponding to the one or more of the bit line pairs of input data having a plurality of bits in a write operation, wherein the write circuit includes a negative potential generating circuit that generates a third potential lower than the second potential, and receives a write mask signal with a plurality of bits each corresponding to respective one of the bit line pairs, the write mask signal indicating an enabled state in which data is to be supplied to the one of the bit line pairs or a disabled state in which no data is to be supplied to the one of the bit line pairs, when the write mask signal indicates the enabled state, the write circuit supplies data to the one of the bit line pairs in accordance with a write clock and activates the negative potential generating circuit so as to supply the third potential generated by the negative potential generating circuit to one of bit lines included in the one of the bit line pairs, the one of the bit lines being supplied with low data, and when the write mask signal indicates the disabled state, the write circuit supplies no data to the one of the bit line pairs and inactivates the negative potential generating circuit. - View Dependent Claims (2, 3, 4)
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5. A method of writing data in a semiconductor memory device including:
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a plurality of bit line pairs; a plurality of word lines; a memory cell array including a plurality of memory cells arranged in an array, each of the plurality of memory cells being provided between a first power supply with a first potential and a second power supply with a second potential lower than the first potential, and being connected to one of the bit line pairs and one of the word lines; and a negative potential generating circuit that generates a third potential lower than the second potential, the method comprising; when data is to be supplied to one or more of the bit line pairs, activating the negative potential generating circuit in accordance with a write clock so as to supply the third potential generated by the negative potential generating circuit to one of bit lines included in the one or more of the bit line pairs, the one of the bit lines being supplied with low data; and when no data is to be supplied to the one or more of the bit line pairs, inactivating the negative potential generating circuit.
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Specification