Three-dimensional vertical NOR flash thin-film transistor strings

• US 10,720,448 B2
• Filed: 02/10/2020
• Issued: 07/21/2020
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/786,828
• Publication Number:
  US 20200176475A1
• Time in Patent Office: 162 Days
• Field of Search: 365 46, 365 94, 365100, 365113, 365129, 365148, 365158, 365163, 257 2- 5, 257 9, 257296, 257310, 257379, 257467, 257E2135, 257E31047, 257E27006, 438 29, 438 95, 438 96, 438166, 438135, 438240, 438259, 438365, 438382, 438482, 438486, 438597, 977754
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operation, the circuitry comprising a plurality of voltage sources or references, and sense amplifiers;

a plurality of groups of thin-film NOR memory strings formed above the planar surface, each group comprising a plurality of thin-film NOR memory strings, and each thin-film NOR memory string having a plurality of thin-film memory transistors formed out of;

(i) a common source region and a common drain region, both extending lengthwise along a first direction substantially perpendicular to the planar surface, (ii) one or more channel regions, each provided between and in contact with both the common drain region and the common source region, and (iii) a one or more stacks of gate electrodes, wherein (a) the gate electrodes in each stack are spaced apart from each other and insulated from each other by a dielectric material along the first direction, and (b) each gate electrode is adjacent one of the channel regions, separated therefrom by a charge-trapping material, each gate electrode extending lengthwise along a second direction substantially parallel the planar surface;

a first plurality of conductor segments each electrically connecting the common drain regions of the thin-film NOR memory strings in a corresponding group of thin-film NOR memory strings;

a second plurality of conductor segments each electrically coupled to one of the sense amplifiers in the circuitry for memory circuit operation;

a plurality of bit-line select transistors, wherein each bit-line select transistor, when biased to a conducting state, connects a corresponding one of the conductor segments in the first plurality of conductor segments to a corresponding one of the conductor segments in the second plurality of conductor segments.

2. The memory structure of claim 1, wherein the first and second pluralities of conductor segments are provided between the plurality of groups of thin-film NOR memory strings and the planar surface of the semiconductor substrate.

3. The memory structure of claim 1, wherein the bit-line select transistors are formed in the semiconductor substrate.

4. The memory structure of claim 1, wherein the first and second pluralities of conductor segments are provided above the plurality of groups of thin-film NOR memory strings.

5. The memory structure of claim 4, wherein the bit-line select transistors are formed between first and second conductor segments.

6. The memory structure of claim 1, further comprising:

a third plurality of conductor segments each electrically coupled to one of the voltage sources or references; and

a plurality of source line select transistors, wherein each source line select transistor, when biased to a conducting state, electrically couples a plurality of common source regions of the thin-film NOR memory strings in the plurality of groups of thin-film NOR memory strings to a corresponding conductor segment in the third plurality of conductor segments.

7. The memory structure of claim 6, wherein the third plurality of conductor segments are provided above the plurality of groups of thin-film NOR memory strings.

8. The memory structure of claim 6, further comprising a fourth plurality of conductor segments, wherein each conductor segment in the fourth plurality of conductor segments electrically connects the plurality of common source regions coupled to a corresponding one of the source-line select transistors.

9. The memory structure of claim 6, wherein each common source region provides a capacitance that serves as a virtual voltage source during a read, programming, program-inhibit or erase operation.

10. The memory structure of claim 1, further comprising:

a third plurality of conductor segments each electrically coupled to a plurality of common source regions of the thin-film NOR memory strings in the plurality of groups of thin-film NOR memory strings; and

a plurality of dedicated thin-film NOR memory strings (“

charging columns”

) each having a common source region electrically coupled to a corresponding one of the conductor segments in the third plurality of conductor segments and a common drain region electrically coupled to a selected one of the voltage references, wherein each charging column provides a current drawn from the selected voltage reference to pre-charge the plurality of common source regions prior to a read, programming or erase operation.

11. The memory structure of claim 10, wherein each charging column is formed between two neighboring conductor segments in the third plurality of conductor segments.

12. The memory structure of claim 10, wherein one or more of the thin-film memory transistors in each charging column are conducting during the pre-charging.

13. The memory structure of claim 10, further comprising, for each charging column, a source-line select transistor that connected the selected voltage segment in the semiconductor substrate to the conductor segment corresponding to the charging column in the third plurality of conductor segments.

14. The memory structure of claim 1, wherein the thin-film NOR memory strings are organized in rows and columns, each row extending along a third direction substantially orthogonal to both the first and second directions.

15. The memory structure of claim 1, wherein the sense amplifiers in the circuitry for memory operations are distributed throughout the planar surface of the semiconductor substrate.

16. The memory structure of claim 1, further comprising in each thin-film NOR memory string a pre-charge transistor that, when biased to a conductor state, electrically connects the common source region of and the common drain region.

17. The memory structure of claim 1, wherein the circuitry for memory operation comprises a body bias voltage source, wherein the channel regions of the thin-film NOR memory strings are connected to the body bias voltage source.

18. The memory structure of claim 1, wherein the thin-film NOR memory strings are isolated from each other by an isolation dielectric material or by an air gap.

19. The memory structure of claim 1, wherein the gate electrodes are insulated from each other by an isolation dielectric material or air gap.

20. The memory structure of claim 3, wherein the gate electrodes of each stack terminate at a staircase structure and wherein each gate electrode is electrically coupled at the stair-case structure by vias to the circuitry for memory operations.

21. A composite memory structure comprising first and second modular memory structures provided one on top of the other, wherein each modular memory structure comprises a memory structure as in the memory structure of claim 1.

22. The composite memory structure of claim 21, wherein the first and second modular memory structures are isolated from each other by a dielectric layer.

23. The composite memory structure of claim 21, wherein the thin-film NOR memory strings in the first and second modular memory structures are aligned along the first direction and wherein in the common source regions of corresponding thin-film NOR memory strings are connected by vias through the dielectric layer.

24. The memory structure of claim 1, further comprising metallic pylons embedded in the common source regions and the common drain region of each thin-film NOR memory string.

25. The memory structure of claim 24, wherein the metallic pylons each comprises one or more of titanium nitride, tungsten nitride or tungsten.

26. The memory structure of claim 25, wherein each metallic pylon is formed using an atomic layer deposition technique.

27. The memory structure of claim 1, wherein the channel regions in each thin-film NOR memory string comprises a first section and a second section, and wherein the first section provide channel regions for the thin-film memory transistors of the thin-film NOR memory string and wherein the second section has a dopant concentration multiple times that of the first section.