Lateral transistors and methods with low-voltage-drop shunt to body diode

• US 10,720,510 B2
• Filed: 05/09/2018
• Issued: 07/21/2020
• Est. Priority Date: 02/13/2012
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun, Blanchard, Richard A.
• Primary Examiner(s): Pizarro, Marcos D.
• Application Number:
  US15/975,284
• Publication Number:
  US 20180323285A1
• Time in Patent Office: 804 Days
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 : Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Claims

1. A power semiconductor device, comprising:

a first and second group of laterally-gated transistors integrated on a single semiconductor die, each said laterally-gated transistor having a first-conductivity-type source region, and a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, and a vertically-extended conduction region connecting a drain region to a drain extension region which is adjacent to said lateral channel;

wherein the threshold voltages of said first group of laterally-gated transistors are lower than the threshold voltages of said second group of laterally-gated transistors;

wherein the vertically-extended conduction region of at least each said second laterally-gated transistor is provided by fixed electrostatic charges in the walls of a trenched field plate, which invert a portion of said body region; and

shielding shapes interposed between the gate electrodes of said laterally-gated transistors.

2. The device of claim 1, wherein said first conductivity type is N type.

3. The device of claim 1, wherein said semiconductor die is made of silicon.

4. A power semiconductor device, comprising:

a first and a second laterally-gated transistor both having a portion of a first-conductivity-type source region, a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, a first-conductivity-type drain extension region connecting said lateral channel to a common drain electrode, and a vertically-extended source extension region connecting said source region to a common source electrode on the backside of the device;

wherein both said gate electrodes are electrically separate portions of a single thin film layer;

wherein the threshold voltage of said first laterally-gated transistor is less than the threshold voltage of said second laterally-gated transistor;

wherein the gate electrode of said first laterally-gated transistor, but not the gate electrode of said second laterally-gated transistor, is connected to said common source electrode; and

wherein said vertically-extended source extension regions are a single common region which laterally separates said first and second laterally-gated transistors.

5. A power semiconductor device, comprising:

a first and a second laterally-gated transistor both having a portion of a first-conductivity-type source region, a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, a first-conductivity-type drain extension region connecting said lateral channel to a common drain electrode, and a vertically-extended source extension region connecting said source region to a common source electrode on the backside of the device;

wherein both said gate electrodes are electrically separate portions of a single thin film layer;

wherein the threshold voltage of said first laterally-gated transistor is less than the threshold voltage of said second laterally-gated transistor;

wherein the gate electrode of said first laterally-gated transistor, but not the gate electrode of said second laterally-gated transistor, is connected to said common source electrode.

6. The device of claim 5, wherein the lateral channel of said first laterally-gated transistor has a shorter lateral extent than does the lateral channel of said second laterally-gated transistor.

7. The device of claim 5, further comprising impurities implanted in the lateral channel of said first laterally-gated transistor which decrease the threshold voltage of said first laterally-gated transistor.

8. The device of claim 5, wherein said laterally-gated transistors both have a first-conductivity-type lateral source extension region laterally connecting said source region to said lateral channel.

9. The device of claim 5, further comprising a shielding shape interposed between said gate electrodes.

10. The device of claim 5, wherein said first conductivity type is N type.