Trench transistors and methods with low-voltage-drop shunt to body diode
First Claim
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1. A power semiconductor device, comprising:
- one or more first trench-gated transistors, each having a portion of a first-conductivity-type source region, and a first gate electrode which is capacitively coupled to a first body region to selectably form a first channel region therein;
one or more second trench-gated transistors, each having a portion of said first-conductivity-type source region, and a second gate electrode which is capacitively coupled to a second body region to selectably form a second channel region therein;
at least one field plate electrode separating said trench-gated transistors;
wherein said trench-gated transistors are integrated on a single semiconductor die;
wherein said second body regions are deeper than said first body regions, and said second channel regions are longer than said first channel regions; and
wherein each said first trench-gated transistor has a lower threshold voltage than each said second trench-gated transistor.
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Abstract
Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
25 Citations
20 Claims
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1. A power semiconductor device, comprising:
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one or more first trench-gated transistors, each having a portion of a first-conductivity-type source region, and a first gate electrode which is capacitively coupled to a first body region to selectably form a first channel region therein; one or more second trench-gated transistors, each having a portion of said first-conductivity-type source region, and a second gate electrode which is capacitively coupled to a second body region to selectably form a second channel region therein; at least one field plate electrode separating said trench-gated transistors; wherein said trench-gated transistors are integrated on a single semiconductor die; wherein said second body regions are deeper than said first body regions, and said second channel regions are longer than said first channel regions; and wherein each said first trench-gated transistor has a lower threshold voltage than each said second trench-gated transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A power semiconductor device, comprising:
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one or more first trench-gated transistors, each having a portion of a first-conductivity-type source region, and a first gate electrode which is capacitively coupled to a first body region to selectably form a first channel region therein, and a drain region; one or more second trench-gated transistors, each having another portion of said first-conductivity-type source region, and a second gate electrode which is capacitively coupled to a second body region to selectably form a second channel region therein, and a drain region; wherein said trench-gated transistors are integrated on a single semiconductor die; wherein said second body regions are deeper than said first body regions, and said second channel regions are longer than said first channel regions; wherein said source regions are connected to a single common source electrode; wherein said drain regions are connected to a single common drain electrode; wherein said second gate electrodes are connected to a single common gate electrode; and wherein said first gate electrodes are connected to said common source electrode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A power semiconductor device, comprising:
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a first and second gated transistor, integrated on a single semiconductor die, both having a first-conductivity-type source region and a gate electrode which is capacitively coupled to a body region to selectably form a channel region therein; wherein the channel region of said first gated transistor has a shorter spatial extent than does the channel region of said second gated transistor. - View Dependent Claims (20)
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Specification