Adaptive continuous time linear equalization and channel bandwidth control

• US 10,721,106 B1
• Filed: 04/08/2019
• Issued: 07/21/2020
• Est. Priority Date: 04/08/2019
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Hormati, Ali
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US16/378,537
• Time in Patent Office: 470 Days
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03267 with decision feedback equalisers
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

Methods and systems are described for sampling an equalized information signal to generate a sequence of data-pattern-verified edge samples and data decisions, determining a correlation between each data-pattern-verified edge sample and a corresponding penultimate prior data decision of the data decisions, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.

Claims

1. A method comprising:

sampling an equalized information signal to generate a sequence of data-pattern-verified edge samples and data decisions;

determining a correlation between each data-pattern-verified edge sample and a corresponding penultimate prior data decision of the data decisions; and

adjusting, responsive to the correlation, a continuous time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.

2. The method of claim 1, wherein generating the data-pattern-verified edge samples and data decisions comprises slicing the equalized information signal against a pair of speculative decision feedback equalization (DFE) correction factors.

3. The method of claim 1, further comprising generating a decision feedback equalization (DFE)-tap value based on the determined correlation, and wherein adjusting the CTLE code comprises updating the CTLE code based on the generated DFE-tap value.

4. The method of claim 3, wherein generating the DFE-tap value comprises forming respective comparisons between each data-pattern-verified edge sample and the corresponding penultimate prior data decision of the data decisions.

5. The method of claim 1, further decreasing a channel bandwidth setting responsive to a comparison of the CTLE code to a minimum equalization threshold.

6. The method of claim 5, wherein decreasing the channel bandwidth setting comprises adjusting a resistive component of an amplifier.

7. The method of claim 1, wherein determining the correlation comprises forming respective comparisons between each data-pattern-verified edge sample and the corresponding penultimate prior data decision of the data decisions.

8. The method of claim 7, wherein adjusting the CTLE code of the CTLE comprises accumulating the comparisons.

9. The method of claim 8, wherein the comparisons are accumulated in a least-significant-bit (LSB) position of a register.

10. The method of claim 9, wherein adjusting the CTLE code comprises modifying a most-significant-bit (MSB) portion responsive to accumulation of changes in the LSB position.

11. An apparatus comprising:

a set of samplers configured to sample an equalized information signal to generate a sequence of data-pattern-verified edge samples and data decisions;

an accumulator configured to determining a correlation between each data-pattern-verified edge sample and a corresponding penultimate prior data decision of the data decisions; and

a continuous time linear equalizer (CTLE) configured to adjust equalization of the equalized information signal according to a CTLE code, the CTLE code updated responsive to the determined correlation.

12. The apparatus of claim 11, wherein the set of samplers is configured to generate the data-pattern-verified edge samples and data decisions by slicing the equalized information signal against a pair of speculative decision feedback equalization (DFE) correction factors.

13. The apparatus of claim 11, further comprising a decision feedback equalization (DFE) circuit configured to generate a DFE-tap value based on the determined correlation, and wherein adjusting the CTLE code comprises updating the CTLE code based on the generated DFE-tap value.

14. The apparatus of claim 13, wherein the DFE circuit is configured to generate the DFE-tap value by forming respective comparisons between each data-pattern-verified edge sample and the corresponding penultimate prior data decision of the data decisions.

15. The apparatus of claim 14, further comprising:

a comparison circuit configured to compare the CTLE code to a minimum equalization threshold; and

an amplifier connected to the CTLE, the amplifier having an adjustable channel bandwidth setting, the channel bandwidth setting decreased responsive to the comparison of the CTLE code to the minimum equalization threshold.

16. The apparatus of claim 15, wherein the amplifier comprises an adjustable resistive component configured to decrease the channel bandwidth setting.

17. The apparatus of claim 16, wherein the amplifier is a passive multi-input comparator.

18. The apparatus of claim 11, wherein the accumulator is configured to determine the correlation by forming respective comparisons between each data-pattern-verified edge sample and the corresponding penultimate prior data decision of the data decisions.

19. The apparatus of claim 18, wherein the accumulator is configured to accumulate the respective comparisons in a least-significant-bit (LSB) position of a register.

20. The apparatus of claim 19, wherein adjusting the CTLE code comprises modifying a most-significant-bit (MSB) portion responsive to accumulation of changes in LSB position.