Determining a power capping signal using direct memory access

• US 10,725,520 B2
• Filed: 06/23/2017
• Issued: 07/28/2020
• Est. Priority Date: 06/23/2017
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Hansen, Peter, Tan, Julie Victoria
• Primary Examiner(s): Yen, Paul
• Application Number:
  US15/631,734
• Publication Number:
  US 20180373303A1
• Time in Patent Office: 1,131 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03M 1/001 Analogue/digital/analogue conversion
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/504 using pulse width modulation

Abstract

Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.

Claims

1. A method comprising:

generating a first hardware trigger by a processor;

in response to the first hardware trigger, obtaining a first analog voltage signal from a first server;

converting, by an analog-to-digital converter (ADC), the first analog voltage signal to a digital output, the first analog voltage signal received at a first ADC channel of a plurality of ADC channels of the ADC;

generating, by the ADC, a second hardware trigger in response to completion of the converting of the first analog voltage signal to the digital output;

in response to the second hardware trigger, providing, by a direct memory access (DMA) engine, the digital output to a programmable logic device in a first DMA operation;

determining, by the programmable logic device, a power capping signal based on the digital output;

providing the power capping signal to the first server;

generating a third hardware trigger subsequent to providing the digital output to the programmable logic device;

in response to the third hardware trigger, providing, by the DMA engine in a second DMA operation, configuration information that selects a second ADC channel of the plurality of ADC channels, the second ADC channel to receive a second analog voltage signal from a second server;

converting, by the ADC, the second analog voltage signal to a second digital output;

generating, by the ADC, a further hardware trigger in response to completion of the converting of the second analog voltage signal to the second digital output;

in response to the further hardware trigger, providing, by the DMA engine, the second digital output to the programmable logic device in a further DMA operation;

determining, by the programmable logic device, a second power capping signal based on the second digital output; and

providing the second power capping signal to the second server.

2. The method of claim 1, wherein the determining of the power capping signal comprises:

determining a pulse-width modulation (PWM) output based on the digital output; and

defining a PWM rate for the first server based on the PWM output.

3. The method of claim 1, wherein the digital output is provided in the first DMA operation to a memory mapped register of the programmable logic device.

4. The method of claim 1, wherein the obtaining of the first analog voltage signal comprises obtaining samples of the first analog voltage signal from the first server.

5. The method of claim 1, wherein the providing of the configuration information alters a state of a multiplexer to select a different ADC channel of the plurality of ADC channels for measurement.

6. The method of claim 4, comprising computing an average of the samples of the first analog voltage signal, and wherein the digital output is based on the average of the samples of the first analog voltage signal.

7. A system comprising:

a programmable logic device;

an analog-to-digital converter (ADC) to;

in response to a first hardware trigger, receive, at a first ADC channel of a plurality of ADC channels of the ADC, a first analog voltage signal from a first server,

convert the first analog voltage signal to a digital output, and

generate a second hardware trigger in response to completion of the converting of the first analog voltage signal to the digital output;

a processor to, in response to the second hardware trigger, provide the digital output to the programmable logic device in a first direct memory access (DMA) operation,

the programmable logic device to;

determine a power capping signal based on the digital output, and

provide the power capping signal to the first server,

wherein the ADC is to generate a third hardware trigger responsive to completion of the first DMA operation,

wherein the processor is to, in response to the third hardware trigger, provide, in a second DMA operation, configuration information that selects a second ADC channel of the plurality of ADC channels, the second ADC channel to receive a second analog voltage signal from a second server,

wherein the ADC is to;

convert the second analog voltage signal to a second digital output, and

generate a further hardware trigger in response to completion of the converting of the second analog voltage signal to the second digital output,

wherein the processor is to, in response to the further hardware trigger, provide the second digital output to the programmable logic device in a further DMA operation,

wherein the programmable logic device is to;

determine a second power capping signal based on the second digital output, and

provide the second power capping signal to the second server.

8. The system of claim 7, wherein the programmable logic device is coupled to the processor via a bus.

9. The system of claim 7, wherein the power capping signal is to regulate power consumption of the first server.

10. The system of claim 7, wherein the processor includes a microcontroller.

11. The system of claim 7, wherein the processor is to provide the digital output to the programmable logic device via a parallel bus.

12. The system of claim 7, wherein the programmable logic device comprises a complex programmable logic device (CPLD).

13. The system of claim 7, wherein the first server comprises a blade server.

14. The system of claim 7, wherein the processor is to provide the digital output in the first DMA operation to a memory mapped register of the programmable logic device.

15. The system of claim 14, wherein the processor is to provide the configuration information in the second DMA operation using a register write.

16. A system comprising:

a programmable logic device;

an analog-to-digital converter (ADC) to;

convert a first analog voltage signal received at a first ADC channel of a plurality of ADC channels of the ADC from a first server to a digital output, in response to a first hardware trigger generated by a hardware timer in a processor, and

generate a second hardware trigger in response to completion of the converting of the first analog voltage signal to the digital output;

a direct memory access (DMA) engine to, in response to the second hardware trigger, transfer the digital output to the programmable logic device in a first DMA operation,

the programmable logic device to determine a power capping signal based on the digital output, and send the power capping signal to the first server,

wherein the ADC is to generate a third hardware trigger subsequent to the transfer of the digital output to the programmable logic device,

wherein the DMA engine is to, in response to the third hardware trigger, provide, in a second DMA operation, configuration information that selects a second ADC channel of the plurality of ADC channels, the second ADC channel to receive a second analog voltage signal from a second server,

wherein the ADC is to;

convert the second analog voltage signal to a second digital output, and

generate a further hardware trigger in response to completion of the converting of the second analog voltage signal to the second digital output,

wherein the DMA engine is to, in response to the further hardware trigger, provide the second digital output to the programmable logic device in a further DMA operation,

wherein the programmable logic device is to;

determine a second power capping signal based on the second digital output, and

provide the second power capping signal to the second server.

17. The system of claim 16, wherein the DMA engine is to perform a DMA write in the second DMA operation to alter a state of a multiplexer to select the second ADC channel for measurement.

18. The system of claim 16, wherein the DMA engine is to reset the hardware timer subsequent to transfer of the configuration information.

19. The system of claim 16, wherein the DMA engine is to write the digital output to a register in the programmable logic device.