Computational memory cell and processing array device using memory cells

• US 10,725,777 B2
• Filed: 09/19/2017
• Issued: 07/28/2020
• Est. Priority Date: 12/06/2016
• Status: Active Grant

• Current Assignee: GSI Technology Incorporated
• Original Assignee: GSI Technology Incorporated
• Inventors: Shu, Lee-Lean, Chang, Chao-Hung, Akerib, Avidan
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/709,382
• Publication Number:
  US 20180158517A1
• Time in Patent Office: 1,043 Days
• Field of Search: 365154, 365205, 365207
• CPC Class Codes: G06F 15/785 with decentralized control, e.g. smart memories
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Claims

1. A processing array, comprising:

a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell, wherein the storage cell of each memory cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate of the first access transistor coupled to a write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate of the second access transistor coupled to a complementary write bit line;

a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;

a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;

a write port with the write word line coupled to a gate of a write port transistor, a drain of the write port transistor coupled to a source of the first access transistor and a source of the second access transistor;

each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;

each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;

wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation; and

wherein the read bit line is capable of being used to provide read access to the storage cell data.

2. A processing array, comprising:

a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell, wherein the storage cell of each memory cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate coupled to a write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate coupled to a complementary write bit line;

a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;

a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;

a write port with the write word line coupled to a gate of a first write port transistor and a gate of a second write port transistor, a drain of the first write port transistor coupled to a source of the first access transistor and a drain of the second write port transistor coupled to a source of the second access transistor;

each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;

each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;

wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation; and

wherein the read bit line is capable of being used to provide read access to the storage cell data.

3. The processing array of claim 2, wherein the storage cell of each memory cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate of the first access transistor being coupled to a write word line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate of the second access transistor being coupled to the write word line.

4. The processing array of claim 2, wherein each memory cell is capable of a selective write operation.

5. The processing array of claim 2, wherein the computational operation is at least one of a boolean AND operation, a boolean NOR operation, a boolean NAND operation and a boolean OR operation.

6. The processing array of claim 2, wherein the processing array is capable of performing read and write logic concurrently.

7. A processing array, comprising:

a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell;

a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;

a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;

each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;

each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;

wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation;

wherein the read bit line is capable of being used to provide read access to the storage cell data; and

wherein the processing array is capable of performing parallel shifting operation.

8. A processing array, comprising:

a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell;

a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;

a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;

each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;

each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;

wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation;

wherein the read bit line is capable of being used to provide read access to the storage cell data; and

wherein the processing array is capable of performing a search operation.

9. The processing array of claim 8, wherein each memory cell is a static random access memory cell.

10. The processing array of claim 9, wherein the static random access memory cell is one of a two port static random access memory cell, a three port static random access memory cell and a four port static random access memory cell.

11. A processing array, comprising:

at least one read bit line;

at least two memory cells connected to the at least one read bit line, each memory cell having a storage cell and an isolation circuit that buffers the storage cell from signals on the at least one read bit line;

a write bit line connected to the at least two memory cells wherein data is written into the storage cell of one or more of the at least two memory cells;

a write port device that buffers the storage cell of each of the plurality of memory cells so that writing of data into any number of storage cells is performed;

wherein the at least two memory cells connected to the at least one read bit line perform a logic operation on the at least one read bit line by turning on the at least two memory cells connected to the at least one read bit line and performing a read of the at least one bit line; and

wherein the read bit line is capable of being used to provide read access to the storage cell data.

12. The processing array of claim 11 further comprising a plurality of memory cells connected to the at least one read bit line to perform the logic function wherein each of the plurality of memory cells being turned on to perform the logic operation does not adversely affect a speed of the logic operation.

13. The processing array of claim 11 further comprising a plurality of memory cells connected to the at least one read bit line and a write bit line connected to the plurality of memory cells wherein data may be written into the storage cell of one or more of the plurality of memory cells.

14. The processing array of claim 11, wherein each memory cell is capable of performing a selective write operation.

15. The processing array of claim 11, wherein the processing array is capable of performing one or more of a boolean AND operation, a boolean OR operation, a boolean NAND operation and a boolean NOR operation.

16. A processing array, comprising:

at least one read bit line;

at least two memory cells connected to the at least one read bit line, each memory cell having a storage cell and an isolation circuit that buffers the storage cell from signals on the at least one read bit line;

wherein the at least two memory cells connected to the at least one read bit line perform a logic operation on the at least one read bit line by turning on the at least two memory cells connected to the at least one read bit line;

wherein the read bit line is capable of being used to provide read access to the storage cell data; and

wherein the processing array is capable of performing parallel shifting operation.

17. A processing array, comprising:

at least one read bit line;

at least two memory cells connected to the at least one read bit line, each memory cell having a storage cell and an isolation circuit that buffers the storage cell from signals on the at least one read bit line;

wherein the at least two memory cells connected to the at least one read bit line perform a logic operation on the at least one read bit line by turning on the at least two memory cells connected to the at least one read bit line;

wherein the read bit line is capable of being used to provide read access to the storage cell data; and

wherein the processing array is capable of performing a search operation.

18. The processing array of claim 17, wherein each memory cell is a static random access memory cell.

19. The processing array of claim 18, wherein each static random access memory cell is one of a two port static random access memory cell, a three port static random access memory cell and a four port static random access memory cell.