Slave-to-slave direct communication

• US 10,725,949 B2
• Filed: 08/28/2018
• Issued: 07/28/2020
• Est. Priority Date: 08/28/2018
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Graif, Sharon, Amarilio, Lior, Gakman, Mark
• Primary Examiner(s): Snyder, Steven G
• Application Number:
  US16/115,388
• Publication Number:
  US 20200073836A1
• Time in Patent Office: 700 Days
• Field of Search: None
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

Claims

1. An apparatus, comprising:

a master comprising a host controller, the host controller being configured to communicate with a first slave and with a second slave via a serial communication bus, in accordance with a serial communication protocol, the master assigning a unique dynamic slave address to each slave,

wherein the host controller comprises

a master-slave module configured to communicate with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication, and

an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication and not wake the master-slave module in a case of the direct communication,

wherein the always-on module is further configured to detect, while the master-slave module is in the low-power mode, an interrupt request and a request for the direct communication between the first slave and the second slave on the serial communication bus and to recognize the request for the direct communication based on a direct communication address that is separate and distinct from the assigned dynamic address.

2. The apparatus of claim 1, wherein the always-on module is further configured to read in, while the master-slave module is in the low-power mode, the request for the direct communication in response to detecting the interrupt request.

3. The apparatus of claim 2, wherein the serial communication bus comprises an Improved Inter Integrated Circuit (I3C) link, the serial communication protocol comprises an I3C protocol, and the interrupt request comprises an in-band interrupt (IBI) request.

4. The apparatus of claim 2, further comprising one of a computing system, an Internet of Things device, and a virtual reality or augmented reality system incorporating the serial communication bus, the first slave, and the second slave.

5. A method for operating a direction communication over a serial communication bus, comprising:

communicating, by a host controller, with a first slave and with a second slave via a serial communication bus, in accordance with a serial communication protocol, wherein the host controller comprises a master-slave module and an always-on module;

assigning, by the host controller, a unique dynamic address to each slave;

entering, by the master-slave module, into a low-power mode;

entering into a direct communication, while the master-slave module is in the low-power mode and not awaken by the always-on module, by the first slave and the second slave;

clocking, by the always-on module, the serial communication bus for the direct communication;

detecting, by the always-on module while the master-slave module is in the low-power mode, an interrupt request and a request for the direct communication between the first slave and the second slave on the serial communication bus; and

recognizing, by the always-on module, the request for the direct communication based on a direct communication address, that is separate and distinct from the assigned dynamic address.

6. The method of claim 5, further comprising:

reading in, by the always-on module while the master-slave module is in the low-power mode, the request for the direct communication in response to detecting the interrupt request.

7. The method of claim 6, wherein the serial communication bus comprises an I3C link, the serial communication protocol comprises an Improved Inter Integrated Circuit (I3C) protocol, and the interrupt request comprises an in-band interrupt (IBI) request.

8. An apparatus, comprising:

a master comprising a host controller,

the host controller being configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address that is assigned by the master, in accordance with a serial communication protocol, the master-slave address being for master-slave communications,

wherein the host controller is configured to detect an interrupt request in accordance with the serial communication protocol and a request for a direct communication between the first slave and the second slave, on the serial communication bus,

wherein the request for the direct communication includes an address that is separate and distinct from the assigned master-slave address.

9. The apparatus of claim 8, wherein request for the direct communication is not part of the serial communication protocol.

10. The apparatus of claim 8, wherein the host controller is further configured to store at least one direct communication address and to determine whether the request for the direct communication indicates the at least one direct communication address.

11. The apparatus of claim 10, wherein the request for the direct communication comprises an address of the second slave and not an address of the first slave, the first slave being requesting the direct communication to the second slave.

12. The apparatus of claim 10, wherein the host controller is further configured to read in the request for the direct communication in response to detecting the interrupt request.

13. The apparatus of claim 12, wherein the host controller is further configured to bypass servicing the interrupt request in accordance with the serial communication protocol, in response to the request for the direct communication indicating the at least one direct communication address.

14. The apparatus of claim 10, wherein the host controller is further configured to store information associated with the at least one direct communication address and to clock the serial communication bus a number of times based on the information associated with the at least one direct communication address for the direct communication.

15. The apparatus of claim 14,

wherein the host controller further comprises a master-slave module and an always-on module, wherein the master-slave module is configured to operate communication with the first slave and with the second slave via the serial communication bus, in accordance with the serial communication protocol, and

the always-on module is configured to detect the interrupt request and the request for the direct communication and to clock the serial communication bus for the direct communication, while the master-slave module is in a low-power mode.

16. The apparatus of claim 14, wherein the serial communication bus comprises an Improved Inter Integrated Circuit (I3C) link, the serial communication protocol comprises an I3C protocol, and the interrupt request comprises an in-band interrupt (IBI) request, and

wherein the host controller is configured to clock the I3C link 9 times to read in the request for the direct communication in response to detecting the interrupt request, immediately following the interrupt request, and

wherein the at least one direct communication address is 7 bits.

17. The apparatus of claim 14, further comprising one of a computing system, an Internet of Things device, and a virtual reality or augmented reality system incorporating the serial communication bus, the first slave, and the second slave.