Trimming MRAM sense amp with offset cancellation

• US 10,726,897 B1
• Filed: 05/14/2019
• Issued: 07/28/2020
• Est. Priority Date: 05/14/2019
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Maffitt, Thomas Martin, Debrosse, John Kenneth, Wordeman, Matthew R
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/411,909
• Time in Patent Office: 441 Days
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 27/022 using a magnetic memory element
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance

Abstract

A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier circuit for sensing a data state of an MRAM data cell. The circuit includes a first leg and a second leg, and is configured to perform a two-phase read including a first phase in which a first transistor is coupled to a reference resistance circuitry and a second transistor is coupled to a data resistance circuitry, and a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry. The circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit. The circuit further includes a comparator circuit configured to output the data state of the data cell.

Claims

1. A sense amplifier circuit for sensing a data state of a data cell, comprising:

a first leg comprising a first transistor and a second leg comprising a second transistor, wherein the sense amplifier circuit is configured to perform a two-phase read comprising;

a first phase in which the first transistor is coupled to a reference resistance circuitry and the second transistor is coupled to a data resistance circuitry, and

a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry;

a reference trim circuitry coupled to the reference resistance circuitry and a data trim circuitry coupled to the data resistance circuitry, the reference trim circuitry and data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit; and

a comparator circuit configured to output the data state of the data cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.

2. The sense amplifier circuit of claim 1, wherein the reference trim circuitry and the data trim circuitry are both resistive circuitry.

3. The sense amplifier circuit of claim 2, wherein the reference trim circuitry is configured in series with the reference resistance circuitry and a reference bitline.

4. The sense amplifier circuit of claim 3, wherein the data trim circuitry is configured in series with the data resistance circuitry and a data bitline.

5. The sense amplifier circuit of claim 2, wherein the resistance provided by the reference trim circuitry and the resistance provided by the data trim circuitry are each independently configurable.

6. The sense amplifier circuit of claim 5, wherein the reference trim circuitry comprises a first plurality of resistive circuitry elements and wherein increasing a number of resistive circuitry elements in the first plurality increases the trim resistance for the sense amplifier circuit.

7. The sense amplifier circuit of claim 6, wherein the number of resistive circuitry elements in the first plurality of resistive circuitry elements relates to a number of steps in a trim range for the sense amplifier circuit.

8. The sense amplifier circuit of claim 7, wherein the reference trim circuitry further comprises a second plurality of resistive circuitry elements connected in parallel with the first plurality of resistive circuitry elements, wherein the sense amplifier circuit is configured to control activation of the second plurality of resistive circuitry elements, and wherein activation of the second plurality of resistive circuitry elements reduces the resistance added by each trim step in the trim range.

9. The sense amplifier circuit of claim 6, wherein the first plurality of resistive circuitry elements comprise Field Effect Transistors (FETs).

10. The sense amplifier circuit of claim 2, wherein increasing the resistance provided by the reference trim circuitry relative to the data trim circuitry modifies operation of the sense amplifier circuit to decrease device mismatch error in the sense amplifier circuit.

11. The sense amplifier circuit of claim 2, wherein configuring the reference trim circuitry and the data trim circuitry to provide the same resistance results in a no-trim state for the sense amplifier circuit.

12. A magnetoresistive random access memory (MRAM) system, comprising:

a plurality of MRAM data cells; and

a sense amplifier circuit for sensing a data state of a data cell of the plurality of MRAM data cells, the sense amplifier circuit comprising;

a first leg comprising a first transistor and a second leg comprising a second transistor, wherein the sense amplifier circuit is configured to perform a two-phase read comprising;

a first phase in which the first transistor is coupled to a reference resistance circuitry and the second transistor is coupled to a data resistance circuitry, and

a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry;

a reference trim circuitry coupled to the reference resistance circuitry and a data trim circuitry coupled to the data resistance circuitry, the reference trim circuitry and data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit; and

a comparator circuit configured to output the data state of the data cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.

13. The MRAM system of claim 12,

wherein the reference trim circuitry and the data trim circuitry are both resistive circuitry,

wherein the reference trim circuitry is configured in series with the reference resistance circuitry and a reference bitline, and

wherein the data trim circuitry is configured in series with the data resistance circuitry and a data bitline.

14. The MRAM system of claim 12,

wherein the resistance provided by the reference trim circuitry and the resistance provided by the data trim circuitry are each independently configurable,

wherein the reference trim circuitry comprises a first plurality of resistive circuitry elements, and

wherein increasing a number of resistive circuitry elements in the first plurality increases the trim resistance for the sense amplifier circuit.

15. The MRAM system of claim 14,

wherein the number of resistive circuitry elements in the first plurality of resistive circuitry elements relates to a number of steps in a trim range for the sense amplifier circuit,

wherein the reference trim circuitry further comprises a second plurality of resistive circuitry elements connected in parallel with the first plurality of resistive circuitry elements,

wherein the sense amplifier circuit is configured to control activation of the second plurality of resistive circuitry elements, and

wherein activation of the second plurality of resistive circuitry elements reduces the resistance added by each trim step in the trim range.

16. A method of reading data from a magnetoresistive random access memory (MRAM) system, comprising:

performing a two phase read of a data state of a data cell using a sense amplifier circuit, the sense amplifier circuit comprising;

a first leg comprising a first transistor;

a second leg comprising a second transistor;

a reference trim circuitry;

a data trim circuitry; and

a comparator circuit;

wherein during a first phase of the two phase read the first transistor is coupled to a reference resistance circuitry and the second transistor is coupled to a data resistance circuitry,

wherein during a second phase of the two phase read the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry,

wherein the reference trim circuitry is coupled to the reference resistance circuitry and the data trim circuitry is coupled to the data resistance circuitry, the reference trim circuitry and data trim circuitry configured to correct for device mismatch errors relating to the two phase read of the sense amplifier circuit, and

wherein the comparator circuit is configured to output the data state of the data cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.

17. The method of claim 16,

wherein the reference trim circuitry and the data trim circuitry are both resistive circuitry,

wherein the reference trim circuitry is configured in series with the reference resistance circuitry and a reference bitline, and

wherein the data trim circuitry is configured in series with the data resistance circuitry and a data bitline.

18. The method of claim 16,

wherein the resistance provided by the reference trim circuitry and the resistance provided by the data trim circuitry are each independently configurable,

wherein the reference trim circuitry comprises a first plurality of resistive circuitry elements, and

wherein increasing a number of resistive circuitry elements in the first plurality increases the trim resistance for the sense amplifier circuit.

19. The method of claim 18,

wherein the number of resistive circuitry elements in the first plurality of resistive circuitry elements relates to a number of steps in a trim range for the sense amplifier circuit,

wherein the reference trim circuitry further comprises a second plurality of resistive circuitry elements connected in parallel with the first plurality of resistive circuitry elements,

wherein the sense amplifier circuit is configured to control activation of the second plurality of resistive circuitry elements, and

wherein activation of the second plurality of resistive circuitry elements reduces the resistance added by each trim step in the trim range.

20. The method of claim 16,

wherein the reference trim circuitry and the data trim circuitry are both resistive circuitry, and

wherein increasing the resistance provided by the reference trim circuitry relative to the data trim circuitry modifies operation of the sense amplifier circuit to decrease device mismatch error in the sense amplifier circuit.